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SystemView Application v1.0
STM32F411CE SEGGER SystemView Real-time Analysis with OLED Display
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Macros | |
| #define | ADC_SR_AWD ((uint8_t)0x01) |
| #define | ADC_SR_EOC ((uint8_t)0x02) |
| #define | ADC_SR_JEOC ((uint8_t)0x04) |
| #define | ADC_SR_JSTRT ((uint8_t)0x08) |
| #define | ADC_SR_STRT ((uint8_t)0x10) |
| #define | ADC_SR_OVR ((uint8_t)0x20) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR1_RES ((uint32_t)0x03000000) |
| #define | ADC_CR1_RES_0 ((uint32_t)0x01000000) |
| #define | ADC_CR1_RES_1 ((uint32_t)0x02000000) |
| #define | ADC_CR1_OVRIE ((uint32_t)0x04000000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_DDS ((uint32_t)0x00000200) |
| #define | ADC_CR2_EOCS ((uint32_t)0x00000400) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) |
| #define | ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) |
| #define | ADC_CR2_JEXTEN ((uint32_t)0x00300000) |
| #define | ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) |
| #define | ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x0F000000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) |
| #define | ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) |
| #define | ADC_CR2_EXTEN ((uint32_t)0x30000000) |
| #define | ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) |
| #define | ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x40000000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP18 ((uint32_t)0x07000000) |
| #define | ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) |
| #define | ADC_HTR_HT ((uint16_t)0x0FFF) |
| #define | ADC_LTR_LT ((uint16_t)0x0FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR2_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR3_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR4_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
| #define | ADC_CSR_AWD1 ((uint32_t)0x00000001) |
| #define | ADC_CSR_EOC1 ((uint32_t)0x00000002) |
| #define | ADC_CSR_JEOC1 ((uint32_t)0x00000004) |
| #define | ADC_CSR_JSTRT1 ((uint32_t)0x00000008) |
| #define | ADC_CSR_STRT1 ((uint32_t)0x00000010) |
| #define | ADC_CSR_OVR1 ((uint32_t)0x00000020) |
| #define | ADC_CSR_AWD2 ((uint32_t)0x00000100) |
| #define | ADC_CSR_EOC2 ((uint32_t)0x00000200) |
| #define | ADC_CSR_JEOC2 ((uint32_t)0x00000400) |
| #define | ADC_CSR_JSTRT2 ((uint32_t)0x00000800) |
| #define | ADC_CSR_STRT2 ((uint32_t)0x00001000) |
| #define | ADC_CSR_OVR2 ((uint32_t)0x00002000) |
| #define | ADC_CSR_AWD3 ((uint32_t)0x00010000) |
| #define | ADC_CSR_EOC3 ((uint32_t)0x00020000) |
| #define | ADC_CSR_JEOC3 ((uint32_t)0x00040000) |
| #define | ADC_CSR_JSTRT3 ((uint32_t)0x00080000) |
| #define | ADC_CSR_STRT3 ((uint32_t)0x00100000) |
| #define | ADC_CSR_OVR3 ((uint32_t)0x00200000) |
| #define | ADC_CSR_DOVR1 ADC_CSR_OVR1 |
| #define | ADC_CSR_DOVR2 ADC_CSR_OVR2 |
| #define | ADC_CSR_DOVR3 ADC_CSR_OVR3 |
| #define | ADC_CCR_MULTI ((uint32_t)0x0000001F) |
| #define | ADC_CCR_MULTI_0 ((uint32_t)0x00000001) |
| #define | ADC_CCR_MULTI_1 ((uint32_t)0x00000002) |
| #define | ADC_CCR_MULTI_2 ((uint32_t)0x00000004) |
| #define | ADC_CCR_MULTI_3 ((uint32_t)0x00000008) |
| #define | ADC_CCR_MULTI_4 ((uint32_t)0x00000010) |
| #define | ADC_CCR_DELAY ((uint32_t)0x00000F00) |
| #define | ADC_CCR_DELAY_0 ((uint32_t)0x00000100) |
| #define | ADC_CCR_DELAY_1 ((uint32_t)0x00000200) |
| #define | ADC_CCR_DELAY_2 ((uint32_t)0x00000400) |
| #define | ADC_CCR_DELAY_3 ((uint32_t)0x00000800) |
| #define | ADC_CCR_DDS ((uint32_t)0x00002000) |
| #define | ADC_CCR_DMA ((uint32_t)0x0000C000) |
| #define | ADC_CCR_DMA_0 ((uint32_t)0x00004000) |
| #define | ADC_CCR_DMA_1 ((uint32_t)0x00008000) |
| #define | ADC_CCR_ADCPRE ((uint32_t)0x00030000) |
| #define | ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) |
| #define | ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) |
| #define | ADC_CCR_VBATE ((uint32_t)0x00400000) |
| #define | ADC_CCR_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) |
| #define | ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) |
| #define | CAN_MCR_INRQ ((uint16_t)0x0001) |
| #define | CAN_MCR_SLEEP ((uint16_t)0x0002) |
| #define | CAN_MCR_TXFP ((uint16_t)0x0004) |
| #define | CAN_MCR_RFLM ((uint16_t)0x0008) |
| #define | CAN_MCR_NART ((uint16_t)0x0010) |
| #define | CAN_MCR_AWUM ((uint16_t)0x0020) |
| #define | CAN_MCR_ABOM ((uint16_t)0x0040) |
| #define | CAN_MCR_TTCM ((uint16_t)0x0080) |
| #define | CAN_MCR_RESET ((uint16_t)0x8000) |
| #define | CAN_MSR_INAK ((uint16_t)0x0001) |
| #define | CAN_MSR_SLAK ((uint16_t)0x0002) |
| #define | CAN_MSR_ERRI ((uint16_t)0x0004) |
| #define | CAN_MSR_WKUI ((uint16_t)0x0008) |
| #define | CAN_MSR_SLAKI ((uint16_t)0x0010) |
| #define | CAN_MSR_TXM ((uint16_t)0x0100) |
| #define | CAN_MSR_RXM ((uint16_t)0x0200) |
| #define | CAN_MSR_SAMP ((uint16_t)0x0400) |
| #define | CAN_MSR_RX ((uint16_t)0x0800) |
| #define | CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
| #define | CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
| #define | CAN_TSR_ALST0 ((uint32_t)0x00000004) |
| #define | CAN_TSR_TERR0 ((uint32_t)0x00000008) |
| #define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
| #define | CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
| #define | CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
| #define | CAN_TSR_ALST1 ((uint32_t)0x00000400) |
| #define | CAN_TSR_TERR1 ((uint32_t)0x00000800) |
| #define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
| #define | CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
| #define | CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
| #define | CAN_TSR_ALST2 ((uint32_t)0x00040000) |
| #define | CAN_TSR_TERR2 ((uint32_t)0x00080000) |
| #define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
| #define | CAN_TSR_CODE ((uint32_t)0x03000000) |
| #define | CAN_TSR_TME ((uint32_t)0x1C000000) |
| #define | CAN_TSR_TME0 ((uint32_t)0x04000000) |
| #define | CAN_TSR_TME1 ((uint32_t)0x08000000) |
| #define | CAN_TSR_TME2 ((uint32_t)0x10000000) |
| #define | CAN_TSR_LOW ((uint32_t)0xE0000000) |
| #define | CAN_TSR_LOW0 ((uint32_t)0x20000000) |
| #define | CAN_TSR_LOW1 ((uint32_t)0x40000000) |
| #define | CAN_TSR_LOW2 ((uint32_t)0x80000000) |
| #define | CAN_RF0R_FMP0 ((uint8_t)0x03) |
| #define | CAN_RF0R_FULL0 ((uint8_t)0x08) |
| #define | CAN_RF0R_FOVR0 ((uint8_t)0x10) |
| #define | CAN_RF0R_RFOM0 ((uint8_t)0x20) |
| #define | CAN_RF1R_FMP1 ((uint8_t)0x03) |
| #define | CAN_RF1R_FULL1 ((uint8_t)0x08) |
| #define | CAN_RF1R_FOVR1 ((uint8_t)0x10) |
| #define | CAN_RF1R_RFOM1 ((uint8_t)0x20) |
| #define | CAN_IER_TMEIE ((uint32_t)0x00000001) |
| #define | CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
| #define | CAN_IER_FFIE0 ((uint32_t)0x00000004) |
| #define | CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
| #define | CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
| #define | CAN_IER_FFIE1 ((uint32_t)0x00000020) |
| #define | CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
| #define | CAN_IER_EWGIE ((uint32_t)0x00000100) |
| #define | CAN_IER_EPVIE ((uint32_t)0x00000200) |
| #define | CAN_IER_BOFIE ((uint32_t)0x00000400) |
| #define | CAN_IER_LECIE ((uint32_t)0x00000800) |
| #define | CAN_IER_ERRIE ((uint32_t)0x00008000) |
| #define | CAN_IER_WKUIE ((uint32_t)0x00010000) |
| #define | CAN_IER_SLKIE ((uint32_t)0x00020000) |
| #define | CAN_ESR_EWGF ((uint32_t)0x00000001) |
| #define | CAN_ESR_EPVF ((uint32_t)0x00000002) |
| #define | CAN_ESR_BOFF ((uint32_t)0x00000004) |
| #define | CAN_ESR_LEC ((uint32_t)0x00000070) |
| #define | CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
| #define | CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
| #define | CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
| #define | CAN_ESR_TEC ((uint32_t)0x00FF0000) |
| #define | CAN_ESR_REC ((uint32_t)0xFF000000) |
| #define | CAN_BTR_BRP ((uint32_t)0x000003FF) |
| #define | CAN_BTR_TS1 ((uint32_t)0x000F0000) |
| #define | CAN_BTR_TS2 ((uint32_t)0x00700000) |
| #define | CAN_BTR_SJW ((uint32_t)0x03000000) |
| #define | CAN_BTR_LBKM ((uint32_t)0x40000000) |
| #define | CAN_BTR_SILM ((uint32_t)0x80000000) |
| #define | CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT0R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT1R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI2R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI2R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI2R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT2R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_FMR_FINIT ((uint8_t)0x01) |
| #define | CAN_FM1R_FBM ((uint16_t)0x3FFF) |
| #define | CAN_FM1R_FBM0 ((uint16_t)0x0001) |
| #define | CAN_FM1R_FBM1 ((uint16_t)0x0002) |
| #define | CAN_FM1R_FBM2 ((uint16_t)0x0004) |
| #define | CAN_FM1R_FBM3 ((uint16_t)0x0008) |
| #define | CAN_FM1R_FBM4 ((uint16_t)0x0010) |
| #define | CAN_FM1R_FBM5 ((uint16_t)0x0020) |
| #define | CAN_FM1R_FBM6 ((uint16_t)0x0040) |
| #define | CAN_FM1R_FBM7 ((uint16_t)0x0080) |
| #define | CAN_FM1R_FBM8 ((uint16_t)0x0100) |
| #define | CAN_FM1R_FBM9 ((uint16_t)0x0200) |
| #define | CAN_FM1R_FBM10 ((uint16_t)0x0400) |
| #define | CAN_FM1R_FBM11 ((uint16_t)0x0800) |
| #define | CAN_FM1R_FBM12 ((uint16_t)0x1000) |
| #define | CAN_FM1R_FBM13 ((uint16_t)0x2000) |
| #define | CAN_FS1R_FSC ((uint16_t)0x3FFF) |
| #define | CAN_FS1R_FSC0 ((uint16_t)0x0001) |
| #define | CAN_FS1R_FSC1 ((uint16_t)0x0002) |
| #define | CAN_FS1R_FSC2 ((uint16_t)0x0004) |
| #define | CAN_FS1R_FSC3 ((uint16_t)0x0008) |
| #define | CAN_FS1R_FSC4 ((uint16_t)0x0010) |
| #define | CAN_FS1R_FSC5 ((uint16_t)0x0020) |
| #define | CAN_FS1R_FSC6 ((uint16_t)0x0040) |
| #define | CAN_FS1R_FSC7 ((uint16_t)0x0080) |
| #define | CAN_FS1R_FSC8 ((uint16_t)0x0100) |
| #define | CAN_FS1R_FSC9 ((uint16_t)0x0200) |
| #define | CAN_FS1R_FSC10 ((uint16_t)0x0400) |
| #define | CAN_FS1R_FSC11 ((uint16_t)0x0800) |
| #define | CAN_FS1R_FSC12 ((uint16_t)0x1000) |
| #define | CAN_FS1R_FSC13 ((uint16_t)0x2000) |
| #define | CAN_FFA1R_FFA ((uint16_t)0x3FFF) |
| #define | CAN_FFA1R_FFA0 ((uint16_t)0x0001) |
| #define | CAN_FFA1R_FFA1 ((uint16_t)0x0002) |
| #define | CAN_FFA1R_FFA2 ((uint16_t)0x0004) |
| #define | CAN_FFA1R_FFA3 ((uint16_t)0x0008) |
| #define | CAN_FFA1R_FFA4 ((uint16_t)0x0010) |
| #define | CAN_FFA1R_FFA5 ((uint16_t)0x0020) |
| #define | CAN_FFA1R_FFA6 ((uint16_t)0x0040) |
| #define | CAN_FFA1R_FFA7 ((uint16_t)0x0080) |
| #define | CAN_FFA1R_FFA8 ((uint16_t)0x0100) |
| #define | CAN_FFA1R_FFA9 ((uint16_t)0x0200) |
| #define | CAN_FFA1R_FFA10 ((uint16_t)0x0400) |
| #define | CAN_FFA1R_FFA11 ((uint16_t)0x0800) |
| #define | CAN_FFA1R_FFA12 ((uint16_t)0x1000) |
| #define | CAN_FFA1R_FFA13 ((uint16_t)0x2000) |
| #define | CAN_FA1R_FACT ((uint16_t)0x3FFF) |
| #define | CAN_FA1R_FACT0 ((uint16_t)0x0001) |
| #define | CAN_FA1R_FACT1 ((uint16_t)0x0002) |
| #define | CAN_FA1R_FACT2 ((uint16_t)0x0004) |
| #define | CAN_FA1R_FACT3 ((uint16_t)0x0008) |
| #define | CAN_FA1R_FACT4 ((uint16_t)0x0010) |
| #define | CAN_FA1R_FACT5 ((uint16_t)0x0020) |
| #define | CAN_FA1R_FACT6 ((uint16_t)0x0040) |
| #define | CAN_FA1R_FACT7 ((uint16_t)0x0080) |
| #define | CAN_FA1R_FACT8 ((uint16_t)0x0100) |
| #define | CAN_FA1R_FACT9 ((uint16_t)0x0200) |
| #define | CAN_FA1R_FACT10 ((uint16_t)0x0400) |
| #define | CAN_FA1R_FACT11 ((uint16_t)0x0800) |
| #define | CAN_FA1R_FACT12 ((uint16_t)0x1000) |
| #define | CAN_FA1R_FACT13 ((uint16_t)0x2000) |
| #define | CAN_F0R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F0R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R2_FB31 ((uint32_t)0x80000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint8_t)0xFF) |
| #define | CRC_CR_RESET ((uint8_t)0x01) |
| #define | CRYP_CR_ALGODIR ((uint32_t)0x00000004) |
| #define | CRYP_CR_ALGOMODE ((uint32_t)0x00080038) |
| #define | CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008) |
| #define | CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010) |
| #define | CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020) |
| #define | CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) |
| #define | CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008) |
| #define | CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010) |
| #define | CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018) |
| #define | CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020) |
| #define | CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028) |
| #define | CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030) |
| #define | CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038) |
| #define | CRYP_CR_DATATYPE ((uint32_t)0x000000C0) |
| #define | CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040) |
| #define | CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080) |
| #define | CRYP_CR_KEYSIZE ((uint32_t)0x00000300) |
| #define | CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100) |
| #define | CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200) |
| #define | CRYP_CR_FFLUSH ((uint32_t)0x00004000) |
| #define | CRYP_CR_CRYPEN ((uint32_t)0x00008000) |
| #define | CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000) |
| #define | CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000) |
| #define | CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000) |
| #define | CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) |
| #define | CRYP_SR_IFEM ((uint32_t)0x00000001) |
| #define | CRYP_SR_IFNF ((uint32_t)0x00000002) |
| #define | CRYP_SR_OFNE ((uint32_t)0x00000004) |
| #define | CRYP_SR_OFFU ((uint32_t)0x00000008) |
| #define | CRYP_SR_BUSY ((uint32_t)0x00000010) |
| #define | CRYP_DMACR_DIEN ((uint32_t)0x00000001) |
| #define | CRYP_DMACR_DOEN ((uint32_t)0x00000002) |
| #define | CRYP_IMSCR_INIM ((uint32_t)0x00000001) |
| #define | CRYP_IMSCR_OUTIM ((uint32_t)0x00000002) |
| #define | CRYP_RISR_OUTRIS ((uint32_t)0x00000001) |
| #define | CRYP_RISR_INRIS ((uint32_t)0x00000002) |
| #define | CRYP_MISR_INMIS ((uint32_t)0x00000001) |
| #define | CRYP_MISR_OUTMIS ((uint32_t)0x00000002) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000U) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) |
| #define | DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) |
| #define | DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) |
| #define | DAC_SR_DMAUDR1 ((uint32_t)0x00002000) |
| #define | DAC_SR_DMAUDR2 ((uint32_t)0x20000000) |
| #define | DCMI_CR_CAPTURE ((uint32_t)0x00000001) |
| #define | DCMI_CR_CM ((uint32_t)0x00000002) |
| #define | DCMI_CR_CROP ((uint32_t)0x00000004) |
| #define | DCMI_CR_JPEG ((uint32_t)0x00000008) |
| #define | DCMI_CR_ESS ((uint32_t)0x00000010) |
| #define | DCMI_CR_PCKPOL ((uint32_t)0x00000020) |
| #define | DCMI_CR_HSPOL ((uint32_t)0x00000040) |
| #define | DCMI_CR_VSPOL ((uint32_t)0x00000080) |
| #define | DCMI_CR_FCRC_0 ((uint32_t)0x00000100) |
| #define | DCMI_CR_FCRC_1 ((uint32_t)0x00000200) |
| #define | DCMI_CR_EDM_0 ((uint32_t)0x00000400) |
| #define | DCMI_CR_EDM_1 ((uint32_t)0x00000800) |
| #define | DCMI_CR_CRE ((uint32_t)0x00001000) |
| #define | DCMI_CR_ENABLE ((uint32_t)0x00004000) |
| #define | DCMI_SR_HSYNC ((uint32_t)0x00000001) |
| #define | DCMI_SR_VSYNC ((uint32_t)0x00000002) |
| #define | DCMI_SR_FNE ((uint32_t)0x00000004) |
| #define | DCMI_RIS_FRAME_RIS ((uint32_t)0x00000001) |
| #define | DCMI_RIS_OVR_RIS ((uint32_t)0x00000002) |
| #define | DCMI_RIS_ERR_RIS ((uint32_t)0x00000004) |
| #define | DCMI_RIS_VSYNC_RIS ((uint32_t)0x00000008) |
| #define | DCMI_RIS_LINE_RIS ((uint32_t)0x00000010) |
| #define | DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS |
| #define | DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS |
| #define | DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS |
| #define | DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS |
| #define | DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS |
| #define | DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS |
| #define | DCMI_IER_FRAME_IE ((uint32_t)0x00000001) |
| #define | DCMI_IER_OVR_IE ((uint32_t)0x00000002) |
| #define | DCMI_IER_ERR_IE ((uint32_t)0x00000004) |
| #define | DCMI_IER_VSYNC_IE ((uint32_t)0x00000008) |
| #define | DCMI_IER_LINE_IE ((uint32_t)0x00000010) |
| #define | DCMI_IER_OVF_IE DCMI_IER_OVR_IE |
| #define | DCMI_MIS_FRAME_MIS ((uint32_t)0x00000001) |
| #define | DCMI_MIS_OVR_MIS ((uint32_t)0x00000002) |
| #define | DCMI_MIS_ERR_MIS ((uint32_t)0x00000004) |
| #define | DCMI_MIS_VSYNC_MIS ((uint32_t)0x00000008) |
| #define | DCMI_MIS_LINE_MIS ((uint32_t)0x00000010) |
| #define | DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS |
| #define | DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS |
| #define | DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS |
| #define | DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS |
| #define | DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS |
| #define | DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001) |
| #define | DCMI_ICR_OVR_ISC ((uint32_t)0x00000002) |
| #define | DCMI_ICR_ERR_ISC ((uint32_t)0x00000004) |
| #define | DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008) |
| #define | DCMI_ICR_LINE_ISC ((uint32_t)0x00000010) |
| #define | DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC |
| #define | DCMI_ESCR_FSC ((uint32_t)0x000000FF) |
| #define | DCMI_ESCR_LSC ((uint32_t)0x0000FF00) |
| #define | DCMI_ESCR_LEC ((uint32_t)0x00FF0000) |
| #define | DCMI_ESCR_FEC ((uint32_t)0xFF000000) |
| #define | DCMI_ESUR_FSU ((uint32_t)0x000000FF) |
| #define | DCMI_ESUR_LSU ((uint32_t)0x0000FF00) |
| #define | DCMI_ESUR_LEU ((uint32_t)0x00FF0000) |
| #define | DCMI_ESUR_FEU ((uint32_t)0xFF000000) |
| #define | DCMI_CWSTRT_HOFFCNT ((uint32_t)0x00003FFF) |
| #define | DCMI_CWSTRT_VST ((uint32_t)0x1FFF0000) |
| #define | DCMI_CWSIZE_CAPCNT ((uint32_t)0x00003FFF) |
| #define | DCMI_CWSIZE_VLINE ((uint32_t)0x3FFF0000) |
| #define | DCMI_DR_BYTE0 ((uint32_t)0x000000FF) |
| #define | DCMI_DR_BYTE1 ((uint32_t)0x0000FF00) |
| #define | DCMI_DR_BYTE2 ((uint32_t)0x00FF0000) |
| #define | DCMI_DR_BYTE3 ((uint32_t)0xFF000000) |
| #define | DFSDM_CHCFGR1_DFSDMEN ((uint32_t)0x80000000) |
| #define | DFSDM_CHCFGR1_CKOUTSRC ((uint32_t)0x40000000) |
| #define | DFSDM_CHCFGR1_CKOUTDIV ((uint32_t)0x00FF0000) |
| #define | DFSDM_CHCFGR1_DATPACK ((uint32_t)0x0000C000) |
| #define | DFSDM_CHCFGR1_DATPACK_1 ((uint32_t)0x00008000) |
| #define | DFSDM_CHCFGR1_DATPACK_0 ((uint32_t)0x00004000) |
| #define | DFSDM_CHCFGR1_DATMPX ((uint32_t)0x00003000) |
| #define | DFSDM_CHCFGR1_DATMPX_1 ((uint32_t)0x00002000) |
| #define | DFSDM_CHCFGR1_DATMPX_0 ((uint32_t)0x00001000) |
| #define | DFSDM_CHCFGR1_CHINSEL ((uint32_t)0x00000100) |
| #define | DFSDM_CHCFGR1_CHEN ((uint32_t)0x00000080) |
| #define | DFSDM_CHCFGR1_CKABEN ((uint32_t)0x00000040) |
| #define | DFSDM_CHCFGR1_SCDEN ((uint32_t)0x00000020) |
| #define | DFSDM_CHCFGR1_SPICKSEL ((uint32_t)0x0000000C) |
| #define | DFSDM_CHCFGR1_SPICKSEL_1 ((uint32_t)0x00000008) |
| #define | DFSDM_CHCFGR1_SPICKSEL_0 ((uint32_t)0x00000004) |
| #define | DFSDM_CHCFGR1_SITP ((uint32_t)0x00000003) |
| #define | DFSDM_CHCFGR1_SITP_1 ((uint32_t)0x00000002) |
| #define | DFSDM_CHCFGR1_SITP_0 ((uint32_t)0x00000001) |
| #define | DFSDM_CHCFGR2_OFFSET ((uint32_t)0xFFFFFF00) |
| #define | DFSDM_CHCFGR2_DTRBS ((uint32_t)0x000000F8) |
| #define | DFSDM_CHAWSCDR_AWFORD ((uint32_t)0x00C00000) |
| #define | DFSDM_CHAWSCDR_AWFORD_1 ((uint32_t)0x00800000) |
| #define | DFSDM_CHAWSCDR_AWFORD_0 ((uint32_t)0x00400000) |
| #define | DFSDM_CHAWSCDR_AWFOSR ((uint32_t)0x001F0000) |
| #define | DFSDM_CHAWSCDR_BKSCD ((uint32_t)0x0000F000) |
| #define | DFSDM_CHAWSCDR_SCDT ((uint32_t)0x000000FF) |
| #define | DFSDM_CHWDATR_WDATA ((uint32_t)0x0000FFFF) |
| #define | DFSDM_CHDATINR_INDAT0 ((uint32_t)0x0000FFFF) |
| #define | DFSDM_CHDATINR_INDAT1 ((uint32_t)0xFFFF0000) |
| #define | DFSDM_FLTCR1_AWFSEL ((uint32_t)0x40000000) |
| #define | DFSDM_FLTCR1_FAST ((uint32_t)0x20000000) |
| #define | DFSDM_FLTCR1_RCH ((uint32_t)0x07000000) |
| #define | DFSDM_FLTCR1_RDMAEN ((uint32_t)0x00200000) |
| #define | DFSDM_FLTCR1_RSYNC ((uint32_t)0x00080000) |
| #define | DFSDM_FLTCR1_RCONT ((uint32_t)0x00040000) |
| #define | DFSDM_FLTCR1_RSWSTART ((uint32_t)0x00020000) |
| #define | DFSDM_FLTCR1_JEXTEN ((uint32_t)0x00006000) |
| #define | DFSDM_FLTCR1_JEXTEN_1 ((uint32_t)0x00004000) |
| #define | DFSDM_FLTCR1_JEXTEN_0 ((uint32_t)0x00002000) |
| #define | DFSDM_FLTCR1_JEXTSEL ((uint32_t)0x00000700) |
| #define | DFSDM_FLTCR1_JEXTSEL_2 ((uint32_t)0x00000400) |
| #define | DFSDM_FLTCR1_JEXTSEL_1 ((uint32_t)0x00000200) |
| #define | DFSDM_FLTCR1_JEXTSEL_0 ((uint32_t)0x00000100) |
| #define | DFSDM_FLTCR1_JDMAEN ((uint32_t)0x00000020) |
| #define | DFSDM_FLTCR1_JSCAN ((uint32_t)0x00000010) |
| #define | DFSDM_FLTCR1_JSYNC ((uint32_t)0x00000008) |
| #define | DFSDM_FLTCR1_JSWSTART ((uint32_t)0x00000002) |
| #define | DFSDM_FLTCR1_DFEN ((uint32_t)0x00000001) |
| #define | DFSDM_FLTCR2_AWDCH ((uint32_t)0x000F0000) |
| #define | DFSDM_FLTCR2_EXCH ((uint32_t)0x00000F00) |
| #define | DFSDM_FLTCR2_CKABIE ((uint32_t)0x00000040) |
| #define | DFSDM_FLTCR2_SCDIE ((uint32_t)0x00000020) |
| #define | DFSDM_FLTCR2_AWDIE ((uint32_t)0x00000010) |
| #define | DFSDM_FLTCR2_ROVRIE ((uint32_t)0x00000008) |
| #define | DFSDM_FLTCR2_JOVRIE ((uint32_t)0x00000004) |
| #define | DFSDM_FLTCR2_REOCIE ((uint32_t)0x00000002) |
| #define | DFSDM_FLTCR2_JEOCIE ((uint32_t)0x00000001) |
| #define | DFSDM_FLTISR_SCDF ((uint32_t)0x0F000000) |
| #define | DFSDM_FLTISR_CKABF ((uint32_t)0x000F0000) |
| #define | DFSDM_FLTISR_RCIP ((uint32_t)0x00004000) |
| #define | DFSDM_FLTISR_JCIP ((uint32_t)0x00002000) |
| #define | DFSDM_FLTISR_AWDF ((uint32_t)0x00000010) |
| #define | DFSDM_FLTISR_ROVRF ((uint32_t)0x00000008) |
| #define | DFSDM_FLTISR_JOVRF ((uint32_t)0x00000004) |
| #define | DFSDM_FLTISR_REOCF ((uint32_t)0x00000002) |
| #define | DFSDM_FLTISR_JEOCF ((uint32_t)0x00000001) |
| #define | DFSDM_FLTICR_CLRSCSDF ((uint32_t)0x0F000000) |
| #define | DFSDM_FLTICR_CLRCKABF ((uint32_t)0x000F0000) |
| #define | DFSDM_FLTICR_CLRROVRF ((uint32_t)0x00000008) |
| #define | DFSDM_FLTICR_CLRJOVRF ((uint32_t)0x00000004) |
| #define | DFSDM_FLTJCHGR_JCHG ((uint32_t)0x000000FF) |
| #define | DFSDM_FLTFCR_FORD ((uint32_t)0xE0000000) |
| #define | DFSDM_FLTFCR_FORD_2 ((uint32_t)0x80000000) |
| #define | DFSDM_FLTFCR_FORD_1 ((uint32_t)0x40000000) |
| #define | DFSDM_FLTFCR_FORD_0 ((uint32_t)0x20000000) |
| #define | DFSDM_FLTFCR_FOSR ((uint32_t)0x03FF0000) |
| #define | DFSDM_FLTFCR_IOSR ((uint32_t)0x000000FF) |
| #define | DFSDM_FLTJDATAR_JDATA ((uint32_t)0xFFFFFF00) |
| #define | DFSDM_FLTJDATAR_JDATACH ((uint32_t)0x00000007) |
| #define | DFSDM_FLTRDATAR_RDATA ((uint32_t)0xFFFFFF00) |
| #define | DFSDM_FLTRDATAR_RPEND ((uint32_t)0x00000010) |
| #define | DFSDM_FLTRDATAR_RDATACH ((uint32_t)0x00000007) |
| #define | DFSDM_FLTAWHTR_AWHT ((uint32_t)0xFFFFFF00) |
| #define | DFSDM_FLTAWHTR_BKAWH ((uint32_t)0x0000000F) |
| #define | DFSDM_FLTAWLTR_AWLT ((uint32_t)0xFFFFFF00) |
| #define | DFSDM_FLTAWLTR_BKAWL ((uint32_t)0x0000000F) |
| #define | DFSDM_FLTAWSR_AWHTF ((uint32_t)0x00000F00) |
| #define | DFSDM_FLTAWSR_AWLTF ((uint32_t)0x0000000F) |
| #define | DFSDM_FLTAWCFR_CLRAWHTF ((uint32_t)0x00000F00) |
| #define | DFSDM_FLTAWCFR_CLRAWLTF ((uint32_t)0x0000000F) |
| #define | DFSDM_FLTEXMAX_EXMAX ((uint32_t)0xFFFFFF00) |
| #define | DFSDM_FLTEXMAX_EXMAXCH ((uint32_t)0x00000007) |
| #define | DFSDM_FLTEXMIN_EXMIN ((uint32_t)0xFFFFFF00) |
| #define | DFSDM_FLTEXMIN_EXMINCH ((uint32_t)0x00000007) |
| #define | DFSDM_FLTCNVTIMR_CNVCNT ((uint32_t)0xFFFFFFF0) |
| #define | DMA_SxCR_CHSEL ((uint32_t)0x0E000000) |
| #define | DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000) |
| #define | DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000) |
| #define | DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) |
| #define | DMA_SxCR_MBURST ((uint32_t)0x01800000) |
| #define | DMA_SxCR_MBURST_0 ((uint32_t)0x00800000) |
| #define | DMA_SxCR_MBURST_1 ((uint32_t)0x01000000) |
| #define | DMA_SxCR_PBURST ((uint32_t)0x00600000) |
| #define | DMA_SxCR_PBURST_0 ((uint32_t)0x00200000) |
| #define | DMA_SxCR_PBURST_1 ((uint32_t)0x00400000) |
| #define | DMA_SxCR_ACK ((uint32_t)0x00100000) |
| #define | DMA_SxCR_CT ((uint32_t)0x00080000) |
| #define | DMA_SxCR_DBM ((uint32_t)0x00040000) |
| #define | DMA_SxCR_PL ((uint32_t)0x00030000) |
| #define | DMA_SxCR_PL_0 ((uint32_t)0x00010000) |
| #define | DMA_SxCR_PL_1 ((uint32_t)0x00020000) |
| #define | DMA_SxCR_PINCOS ((uint32_t)0x00008000) |
| #define | DMA_SxCR_MSIZE ((uint32_t)0x00006000) |
| #define | DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000) |
| #define | DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000) |
| #define | DMA_SxCR_PSIZE ((uint32_t)0x00001800) |
| #define | DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800) |
| #define | DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000) |
| #define | DMA_SxCR_MINC ((uint32_t)0x00000400) |
| #define | DMA_SxCR_PINC ((uint32_t)0x00000200) |
| #define | DMA_SxCR_CIRC ((uint32_t)0x00000100) |
| #define | DMA_SxCR_DIR ((uint32_t)0x000000C0) |
| #define | DMA_SxCR_DIR_0 ((uint32_t)0x00000040) |
| #define | DMA_SxCR_DIR_1 ((uint32_t)0x00000080) |
| #define | DMA_SxCR_PFCTRL ((uint32_t)0x00000020) |
| #define | DMA_SxCR_TCIE ((uint32_t)0x00000010) |
| #define | DMA_SxCR_HTIE ((uint32_t)0x00000008) |
| #define | DMA_SxCR_TEIE ((uint32_t)0x00000004) |
| #define | DMA_SxCR_DMEIE ((uint32_t)0x00000002) |
| #define | DMA_SxCR_EN ((uint32_t)0x00000001) |
| #define | DMA_SxNDT ((uint32_t)0x0000FFFF) |
| #define | DMA_SxNDT_0 ((uint32_t)0x00000001) |
| #define | DMA_SxNDT_1 ((uint32_t)0x00000002) |
| #define | DMA_SxNDT_2 ((uint32_t)0x00000004) |
| #define | DMA_SxNDT_3 ((uint32_t)0x00000008) |
| #define | DMA_SxNDT_4 ((uint32_t)0x00000010) |
| #define | DMA_SxNDT_5 ((uint32_t)0x00000020) |
| #define | DMA_SxNDT_6 ((uint32_t)0x00000040) |
| #define | DMA_SxNDT_7 ((uint32_t)0x00000080) |
| #define | DMA_SxNDT_8 ((uint32_t)0x00000100) |
| #define | DMA_SxNDT_9 ((uint32_t)0x00000200) |
| #define | DMA_SxNDT_10 ((uint32_t)0x00000400) |
| #define | DMA_SxNDT_11 ((uint32_t)0x00000800) |
| #define | DMA_SxNDT_12 ((uint32_t)0x00001000) |
| #define | DMA_SxNDT_13 ((uint32_t)0x00002000) |
| #define | DMA_SxNDT_14 ((uint32_t)0x00004000) |
| #define | DMA_SxNDT_15 ((uint32_t)0x00008000) |
| #define | DMA_SxFCR_FEIE ((uint32_t)0x00000080) |
| #define | DMA_SxFCR_FS ((uint32_t)0x00000038) |
| #define | DMA_SxFCR_FS_0 ((uint32_t)0x00000008) |
| #define | DMA_SxFCR_FS_1 ((uint32_t)0x00000010) |
| #define | DMA_SxFCR_FS_2 ((uint32_t)0x00000020) |
| #define | DMA_SxFCR_DMDIS ((uint32_t)0x00000004) |
| #define | DMA_SxFCR_FTH ((uint32_t)0x00000003) |
| #define | DMA_SxFCR_FTH_0 ((uint32_t)0x00000001) |
| #define | DMA_SxFCR_FTH_1 ((uint32_t)0x00000002) |
| #define | DMA_LISR_TCIF3 ((uint32_t)0x08000000) |
| #define | DMA_LISR_HTIF3 ((uint32_t)0x04000000) |
| #define | DMA_LISR_TEIF3 ((uint32_t)0x02000000) |
| #define | DMA_LISR_DMEIF3 ((uint32_t)0x01000000) |
| #define | DMA_LISR_FEIF3 ((uint32_t)0x00400000) |
| #define | DMA_LISR_TCIF2 ((uint32_t)0x00200000) |
| #define | DMA_LISR_HTIF2 ((uint32_t)0x00100000) |
| #define | DMA_LISR_TEIF2 ((uint32_t)0x00080000) |
| #define | DMA_LISR_DMEIF2 ((uint32_t)0x00040000) |
| #define | DMA_LISR_FEIF2 ((uint32_t)0x00010000) |
| #define | DMA_LISR_TCIF1 ((uint32_t)0x00000800) |
| #define | DMA_LISR_HTIF1 ((uint32_t)0x00000400) |
| #define | DMA_LISR_TEIF1 ((uint32_t)0x00000200) |
| #define | DMA_LISR_DMEIF1 ((uint32_t)0x00000100) |
| #define | DMA_LISR_FEIF1 ((uint32_t)0x00000040) |
| #define | DMA_LISR_TCIF0 ((uint32_t)0x00000020) |
| #define | DMA_LISR_HTIF0 ((uint32_t)0x00000010) |
| #define | DMA_LISR_TEIF0 ((uint32_t)0x00000008) |
| #define | DMA_LISR_DMEIF0 ((uint32_t)0x00000004) |
| #define | DMA_LISR_FEIF0 ((uint32_t)0x00000001) |
| #define | DMA_HISR_TCIF7 ((uint32_t)0x08000000) |
| #define | DMA_HISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_HISR_TEIF7 ((uint32_t)0x02000000) |
| #define | DMA_HISR_DMEIF7 ((uint32_t)0x01000000) |
| #define | DMA_HISR_FEIF7 ((uint32_t)0x00400000) |
| #define | DMA_HISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_HISR_HTIF6 ((uint32_t)0x00100000) |
| #define | DMA_HISR_TEIF6 ((uint32_t)0x00080000) |
| #define | DMA_HISR_DMEIF6 ((uint32_t)0x00040000) |
| #define | DMA_HISR_FEIF6 ((uint32_t)0x00010000) |
| #define | DMA_HISR_TCIF5 ((uint32_t)0x00000800) |
| #define | DMA_HISR_HTIF5 ((uint32_t)0x00000400) |
| #define | DMA_HISR_TEIF5 ((uint32_t)0x00000200) |
| #define | DMA_HISR_DMEIF5 ((uint32_t)0x00000100) |
| #define | DMA_HISR_FEIF5 ((uint32_t)0x00000040) |
| #define | DMA_HISR_TCIF4 ((uint32_t)0x00000020) |
| #define | DMA_HISR_HTIF4 ((uint32_t)0x00000010) |
| #define | DMA_HISR_TEIF4 ((uint32_t)0x00000008) |
| #define | DMA_HISR_DMEIF4 ((uint32_t)0x00000004) |
| #define | DMA_HISR_FEIF4 ((uint32_t)0x00000001) |
| #define | DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000) |
| #define | DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000) |
| #define | DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000) |
| #define | DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000) |
| #define | DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000) |
| #define | DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000) |
| #define | DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000) |
| #define | DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000) |
| #define | DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000) |
| #define | DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000) |
| #define | DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800) |
| #define | DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400) |
| #define | DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200) |
| #define | DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100) |
| #define | DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040) |
| #define | DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020) |
| #define | DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010) |
| #define | DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008) |
| #define | DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004) |
| #define | DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001) |
| #define | DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000) |
| #define | DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000) |
| #define | DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000) |
| #define | DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000) |
| #define | DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000) |
| #define | DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000) |
| #define | DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000) |
| #define | DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000) |
| #define | DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800) |
| #define | DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400) |
| #define | DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200) |
| #define | DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100) |
| #define | DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040) |
| #define | DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020) |
| #define | DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010) |
| #define | DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008) |
| #define | DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004) |
| #define | DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001) |
| #define | DMA2D_CR_START ((uint32_t)0x00000001) |
| #define | DMA2D_CR_SUSP ((uint32_t)0x00000002) |
| #define | DMA2D_CR_ABORT ((uint32_t)0x00000004) |
| #define | DMA2D_CR_TEIE ((uint32_t)0x00000100) |
| #define | DMA2D_CR_TCIE ((uint32_t)0x00000200) |
| #define | DMA2D_CR_TWIE ((uint32_t)0x00000400) |
| #define | DMA2D_CR_CAEIE ((uint32_t)0x00000800) |
| #define | DMA2D_CR_CTCIE ((uint32_t)0x00001000) |
| #define | DMA2D_CR_CEIE ((uint32_t)0x00002000) |
| #define | DMA2D_CR_MODE ((uint32_t)0x00030000) |
| #define | DMA2D_ISR_TEIF ((uint32_t)0x00000001) |
| #define | DMA2D_ISR_TCIF ((uint32_t)0x00000002) |
| #define | DMA2D_ISR_TWIF ((uint32_t)0x00000004) |
| #define | DMA2D_ISR_CAEIF ((uint32_t)0x00000008) |
| #define | DMA2D_ISR_CTCIF ((uint32_t)0x00000010) |
| #define | DMA2D_ISR_CEIF ((uint32_t)0x00000020) |
| #define | DMA2D_IFCR_CTEIF ((uint32_t)0x00000001) |
| #define | DMA2D_IFCR_CTCIF ((uint32_t)0x00000002) |
| #define | DMA2D_IFCR_CTWIF ((uint32_t)0x00000004) |
| #define | DMA2D_IFCR_CAECIF ((uint32_t)0x00000008) |
| #define | DMA2D_IFCR_CCTCIF ((uint32_t)0x00000010) |
| #define | DMA2D_IFCR_CCEIF ((uint32_t)0x00000020) |
| #define | DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF |
| #define | DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF |
| #define | DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF |
| #define | DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF |
| #define | DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF |
| #define | DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF |
| #define | DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA2D_FGOR_LO ((uint32_t)0x00003FFF) |
| #define | DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA2D_BGOR_LO ((uint32_t)0x00003FFF) |
| #define | DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) |
| #define | DMA2D_FGPFCCR_CM_0 ((uint32_t)0x00000001) |
| #define | DMA2D_FGPFCCR_CM_1 ((uint32_t)0x00000002) |
| #define | DMA2D_FGPFCCR_CM_2 ((uint32_t)0x00000004) |
| #define | DMA2D_FGPFCCR_CM_3 ((uint32_t)0x00000008) |
| #define | DMA2D_FGPFCCR_CM_3 ((uint32_t)0x00000008) |
| #define | DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) |
| #define | DMA2D_FGPFCCR_START ((uint32_t)0x00000020) |
| #define | DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) |
| #define | DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) |
| #define | DMA2D_FGPFCCR_AM_0 ((uint32_t)0x00010000) |
| #define | DMA2D_FGPFCCR_AM_1 ((uint32_t)0x00020000) |
| #define | DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) |
| #define | DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) |
| #define | DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) |
| #define | DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) |
| #define | DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) |
| #define | DMA2D_BGPFCCR_CM_0 ((uint32_t)0x00000001) |
| #define | DMA2D_BGPFCCR_CM_1 ((uint32_t)0x00000002) |
| #define | DMA2D_BGPFCCR_CM_2 ((uint32_t)0x00000004) |
| #define | DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) |
| #define | DMA2D_BGPFCCR_START ((uint32_t)0x00000020) |
| #define | DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) |
| #define | DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) |
| #define | DMA2D_BGPFCCR_AM_0 ((uint32_t)0x00010000) |
| #define | DMA2D_BGPFCCR_AM_1 ((uint32_t)0x00020000) |
| #define | DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) |
| #define | DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) |
| #define | DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) |
| #define | DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) |
| #define | DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA2D_OPFCCR_CM ((uint32_t)0x00000007) |
| #define | DMA2D_OPFCCR_CM_0 ((uint32_t)0x00000001) |
| #define | DMA2D_OPFCCR_CM_1 ((uint32_t)0x00000002) |
| #define | DMA2D_OPFCCR_CM_2 ((uint32_t)0x00000004) |
| #define | DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) |
| #define | DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) |
| #define | DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) |
| #define | DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) |
| #define | DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) |
| #define | DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) |
| #define | DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) |
| #define | DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) |
| #define | DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) |
| #define | DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) |
| #define | DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) |
| #define | DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) |
| #define | DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) |
| #define | DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) |
| #define | DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) |
| #define | DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA2D_OOR_LO ((uint32_t)0x00003FFF) |
| #define | DMA2D_NLR_NL ((uint32_t)0x0000FFFF) |
| #define | DMA2D_NLR_PL ((uint32_t)0x3FFF0000) |
| #define | DMA2D_LWR_LW ((uint32_t)0x0000FFFF) |
| #define | DMA2D_AMTCR_EN ((uint32_t)0x00000001) |
| #define | DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_IMR_MR23 ((uint32_t)0x00800000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR23 ((uint32_t)0x00800000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR23 ((uint32_t)0x00800000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR23 ((uint32_t)0x00800000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR23 ((uint32_t)0x00800000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x0000000F) |
| #define | FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000) |
| #define | FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003) |
| #define | FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004) |
| #define | FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005) |
| #define | FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006) |
| #define | FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008) |
| #define | FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009) |
| #define | FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A) |
| #define | FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B) |
| #define | FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C) |
| #define | FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D) |
| #define | FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E) |
| #define | FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F) |
| #define | FLASH_ACR_PRFTEN ((uint32_t)0x00000100) |
| #define | FLASH_ACR_ICEN ((uint32_t)0x00000200) |
| #define | FLASH_ACR_DCEN ((uint32_t)0x00000400) |
| #define | FLASH_ACR_ICRST ((uint32_t)0x00000800) |
| #define | FLASH_ACR_DCRST ((uint32_t)0x00001000) |
| #define | FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) |
| #define | FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000001) |
| #define | FLASH_SR_SOP ((uint32_t)0x00000002) |
| #define | FLASH_SR_WRPERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_PGAERR ((uint32_t)0x00000020) |
| #define | FLASH_SR_PGPERR ((uint32_t)0x00000040) |
| #define | FLASH_SR_PGSERR ((uint32_t)0x00000080) |
| #define | FLASH_SR_BSY ((uint32_t)0x00010000) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_SER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_MER1 FLASH_CR_MER |
| #define | FLASH_CR_SNB ((uint32_t)0x000000F8) |
| #define | FLASH_CR_SNB_0 ((uint32_t)0x00000008) |
| #define | FLASH_CR_SNB_1 ((uint32_t)0x00000010) |
| #define | FLASH_CR_SNB_2 ((uint32_t)0x00000020) |
| #define | FLASH_CR_SNB_3 ((uint32_t)0x00000040) |
| #define | FLASH_CR_SNB_4 ((uint32_t)0x00000040) |
| #define | FLASH_CR_PSIZE ((uint32_t)0x00000300) |
| #define | FLASH_CR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | FLASH_CR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | FLASH_CR_MER2 ((uint32_t)0x00008000) |
| #define | FLASH_CR_STRT ((uint32_t)0x00010000) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x01000000) |
| #define | FLASH_CR_LOCK ((uint32_t)0x80000000) |
| #define | FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001) |
| #define | FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002) |
| #define | FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004) |
| #define | FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008) |
| #define | FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C) |
| #define | FLASH_OPTCR_BFB2 ((uint32_t)0x00000010) |
| #define | FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020) |
| #define | FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040) |
| #define | FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080) |
| #define | FLASH_OPTCR_RDP ((uint32_t)0x0000FF00) |
| #define | FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100) |
| #define | FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200) |
| #define | FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400) |
| #define | FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800) |
| #define | FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000) |
| #define | FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000) |
| #define | FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000) |
| #define | FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000) |
| #define | FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000) |
| #define | FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000) |
| #define | FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000) |
| #define | FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000) |
| #define | FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000) |
| #define | FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000) |
| #define | FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000) |
| #define | FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000) |
| #define | FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000) |
| #define | FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000) |
| #define | FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000) |
| #define | FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000) |
| #define | FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000) |
| #define | FLASH_OPTCR_DB1M ((uint32_t)0x40000000) |
| #define | FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000) |
| #define | FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000) |
| #define | FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000) |
| #define | FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000) |
| #define | FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000) |
| #define | FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000) |
| #define | FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000) |
| #define | FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000) |
| #define | FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000) |
| #define | FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000) |
| #define | FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000) |
| #define | FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000) |
| #define | FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000) |
| #define | FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000) |
| #define | GPIO_MODER_MODER0 ((uint32_t)0x00000003) |
| #define | GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) |
| #define | GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) |
| #define | GPIO_MODER_MODER1 ((uint32_t)0x0000000C) |
| #define | GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) |
| #define | GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) |
| #define | GPIO_MODER_MODER2 ((uint32_t)0x00000030) |
| #define | GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) |
| #define | GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) |
| #define | GPIO_MODER_MODER3 ((uint32_t)0x000000C0) |
| #define | GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) |
| #define | GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) |
| #define | GPIO_MODER_MODER4 ((uint32_t)0x00000300) |
| #define | GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) |
| #define | GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) |
| #define | GPIO_MODER_MODER5 ((uint32_t)0x00000C00) |
| #define | GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) |
| #define | GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) |
| #define | GPIO_MODER_MODER6 ((uint32_t)0x00003000) |
| #define | GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) |
| #define | GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) |
| #define | GPIO_MODER_MODER7 ((uint32_t)0x0000C000) |
| #define | GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) |
| #define | GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) |
| #define | GPIO_MODER_MODER8 ((uint32_t)0x00030000) |
| #define | GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) |
| #define | GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) |
| #define | GPIO_MODER_MODER9 ((uint32_t)0x000C0000) |
| #define | GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) |
| #define | GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) |
| #define | GPIO_MODER_MODER10 ((uint32_t)0x00300000) |
| #define | GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) |
| #define | GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) |
| #define | GPIO_MODER_MODER11 ((uint32_t)0x00C00000) |
| #define | GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) |
| #define | GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) |
| #define | GPIO_MODER_MODER12 ((uint32_t)0x03000000) |
| #define | GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) |
| #define | GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) |
| #define | GPIO_MODER_MODER13 ((uint32_t)0x0C000000) |
| #define | GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) |
| #define | GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) |
| #define | GPIO_MODER_MODER14 ((uint32_t)0x30000000) |
| #define | GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) |
| #define | GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) |
| #define | GPIO_MODER_MODER15 ((uint32_t)0xC0000000) |
| #define | GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) |
| #define | GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) |
| #define | GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) |
| #define | GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) |
| #define | GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) |
| #define | GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) |
| #define | GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) |
| #define | GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) |
| #define | GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) |
| #define | GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) |
| #define | GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) |
| #define | GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) |
| #define | GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) |
| #define | GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) |
| #define | GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) |
| #define | GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) |
| #define | GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) |
| #define | GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) |
| #define | GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) |
| #define | GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) |
| #define | GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) |
| #define | GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) |
| #define | GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) |
| #define | GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) |
| #define | GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) |
| #define | GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) |
| #define | GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) |
| #define | GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) |
| #define | GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR_0 ((uint32_t)0x00000001) |
| #define | GPIO_IDR_IDR_1 ((uint32_t)0x00000002) |
| #define | GPIO_IDR_IDR_2 ((uint32_t)0x00000004) |
| #define | GPIO_IDR_IDR_3 ((uint32_t)0x00000008) |
| #define | GPIO_IDR_IDR_4 ((uint32_t)0x00000010) |
| #define | GPIO_IDR_IDR_5 ((uint32_t)0x00000020) |
| #define | GPIO_IDR_IDR_6 ((uint32_t)0x00000040) |
| #define | GPIO_IDR_IDR_7 ((uint32_t)0x00000080) |
| #define | GPIO_IDR_IDR_8 ((uint32_t)0x00000100) |
| #define | GPIO_IDR_IDR_9 ((uint32_t)0x00000200) |
| #define | GPIO_IDR_IDR_10 ((uint32_t)0x00000400) |
| #define | GPIO_IDR_IDR_11 ((uint32_t)0x00000800) |
| #define | GPIO_IDR_IDR_12 ((uint32_t)0x00001000) |
| #define | GPIO_IDR_IDR_13 ((uint32_t)0x00002000) |
| #define | GPIO_IDR_IDR_14 ((uint32_t)0x00004000) |
| #define | GPIO_IDR_IDR_15 ((uint32_t)0x00008000) |
| #define | GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 |
| #define | GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 |
| #define | GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 |
| #define | GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 |
| #define | GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 |
| #define | GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 |
| #define | GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 |
| #define | GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 |
| #define | GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 |
| #define | GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 |
| #define | GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 |
| #define | GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 |
| #define | GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 |
| #define | GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 |
| #define | GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 |
| #define | GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 |
| #define | GPIO_ODR_ODR_0 ((uint32_t)0x00000001) |
| #define | GPIO_ODR_ODR_1 ((uint32_t)0x00000002) |
| #define | GPIO_ODR_ODR_2 ((uint32_t)0x00000004) |
| #define | GPIO_ODR_ODR_3 ((uint32_t)0x00000008) |
| #define | GPIO_ODR_ODR_4 ((uint32_t)0x00000010) |
| #define | GPIO_ODR_ODR_5 ((uint32_t)0x00000020) |
| #define | GPIO_ODR_ODR_6 ((uint32_t)0x00000040) |
| #define | GPIO_ODR_ODR_7 ((uint32_t)0x00000080) |
| #define | GPIO_ODR_ODR_8 ((uint32_t)0x00000100) |
| #define | GPIO_ODR_ODR_9 ((uint32_t)0x00000200) |
| #define | GPIO_ODR_ODR_10 ((uint32_t)0x00000400) |
| #define | GPIO_ODR_ODR_11 ((uint32_t)0x00000800) |
| #define | GPIO_ODR_ODR_12 ((uint32_t)0x00001000) |
| #define | GPIO_ODR_ODR_13 ((uint32_t)0x00002000) |
| #define | GPIO_ODR_ODR_14 ((uint32_t)0x00004000) |
| #define | GPIO_ODR_ODR_15 ((uint32_t)0x00008000) |
| #define | GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 |
| #define | GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 |
| #define | GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 |
| #define | GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 |
| #define | GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 |
| #define | GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 |
| #define | GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 |
| #define | GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 |
| #define | GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 |
| #define | GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 |
| #define | GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 |
| #define | GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 |
| #define | GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 |
| #define | GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 |
| #define | GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 |
| #define | GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 |
| #define | GPIO_BSRR_BS_0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS_1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS_2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS_3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS_4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS_5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS_6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS_7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS_8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS_9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS_10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS_11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS_12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS_13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS_14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS_15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR_0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR_1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR_2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR_3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR_4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR_5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR_6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR_7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR_8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR_9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR_10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR_11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR_12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR_13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR_14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR_15 ((uint32_t)0x80000000) |
| #define | HASH_CR_INIT ((uint32_t)0x00000004) |
| #define | HASH_CR_DMAE ((uint32_t)0x00000008) |
| #define | HASH_CR_DATATYPE ((uint32_t)0x00000030) |
| #define | HASH_CR_DATATYPE_0 ((uint32_t)0x00000010) |
| #define | HASH_CR_DATATYPE_1 ((uint32_t)0x00000020) |
| #define | HASH_CR_MODE ((uint32_t)0x00000040) |
| #define | HASH_CR_ALGO ((uint32_t)0x00040080) |
| #define | HASH_CR_ALGO_0 ((uint32_t)0x00000080) |
| #define | HASH_CR_ALGO_1 ((uint32_t)0x00040000) |
| #define | HASH_CR_NBW ((uint32_t)0x00000F00) |
| #define | HASH_CR_NBW_0 ((uint32_t)0x00000100) |
| #define | HASH_CR_NBW_1 ((uint32_t)0x00000200) |
| #define | HASH_CR_NBW_2 ((uint32_t)0x00000400) |
| #define | HASH_CR_NBW_3 ((uint32_t)0x00000800) |
| #define | HASH_CR_DINNE ((uint32_t)0x00001000) |
| #define | HASH_CR_MDMAT ((uint32_t)0x00002000) |
| #define | HASH_CR_LKEY ((uint32_t)0x00010000) |
| #define | HASH_STR_NBW ((uint32_t)0x0000001F) |
| #define | HASH_STR_NBW_0 ((uint32_t)0x00000001) |
| #define | HASH_STR_NBW_1 ((uint32_t)0x00000002) |
| #define | HASH_STR_NBW_2 ((uint32_t)0x00000004) |
| #define | HASH_STR_NBW_3 ((uint32_t)0x00000008) |
| #define | HASH_STR_NBW_4 ((uint32_t)0x00000010) |
| #define | HASH_STR_DCAL ((uint32_t)0x00000100) |
| #define | HASH_IMR_DINIM ((uint32_t)0x00000001) |
| #define | HASH_IMR_DCIM ((uint32_t)0x00000002) |
| #define | HASH_SR_DINIS ((uint32_t)0x00000001) |
| #define | HASH_SR_DCIS ((uint32_t)0x00000002) |
| #define | HASH_SR_DMAS ((uint32_t)0x00000004) |
| #define | HASH_SR_BUSY ((uint32_t)0x00000008) |
| #define | I2C_CR1_PE ((uint16_t)0x0001) |
| #define | I2C_CR1_SMBUS ((uint16_t)0x0002) |
| #define | I2C_CR1_SMBTYPE ((uint16_t)0x0008) |
| #define | I2C_CR1_ENARP ((uint16_t)0x0010) |
| #define | I2C_CR1_ENPEC ((uint16_t)0x0020) |
| #define | I2C_CR1_ENGC ((uint16_t)0x0040) |
| #define | I2C_CR1_NOSTRETCH ((uint16_t)0x0080) |
| #define | I2C_CR1_START ((uint16_t)0x0100) |
| #define | I2C_CR1_STOP ((uint16_t)0x0200) |
| #define | I2C_CR1_ACK ((uint16_t)0x0400) |
| #define | I2C_CR1_POS ((uint16_t)0x0800) |
| #define | I2C_CR1_PEC ((uint16_t)0x1000) |
| #define | I2C_CR1_ALERT ((uint16_t)0x2000) |
| #define | I2C_CR1_SWRST ((uint16_t)0x8000) |
| #define | I2C_CR2_FREQ ((uint16_t)0x003F) |
| #define | I2C_CR2_FREQ_0 ((uint16_t)0x0001) |
| #define | I2C_CR2_FREQ_1 ((uint16_t)0x0002) |
| #define | I2C_CR2_FREQ_2 ((uint16_t)0x0004) |
| #define | I2C_CR2_FREQ_3 ((uint16_t)0x0008) |
| #define | I2C_CR2_FREQ_4 ((uint16_t)0x0010) |
| #define | I2C_CR2_FREQ_5 ((uint16_t)0x0020) |
| #define | I2C_CR2_ITERREN ((uint16_t)0x0100) |
| #define | I2C_CR2_ITEVTEN ((uint16_t)0x0200) |
| #define | I2C_CR2_ITBUFEN ((uint16_t)0x0400) |
| #define | I2C_CR2_DMAEN ((uint16_t)0x0800) |
| #define | I2C_CR2_LAST ((uint16_t)0x1000) |
| #define | I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) |
| #define | I2C_OAR1_ADD8_9 ((uint16_t)0x0300) |
| #define | I2C_OAR1_ADD0 ((uint16_t)0x0001) |
| #define | I2C_OAR1_ADD1 ((uint16_t)0x0002) |
| #define | I2C_OAR1_ADD2 ((uint16_t)0x0004) |
| #define | I2C_OAR1_ADD3 ((uint16_t)0x0008) |
| #define | I2C_OAR1_ADD4 ((uint16_t)0x0010) |
| #define | I2C_OAR1_ADD5 ((uint16_t)0x0020) |
| #define | I2C_OAR1_ADD6 ((uint16_t)0x0040) |
| #define | I2C_OAR1_ADD7 ((uint16_t)0x0080) |
| #define | I2C_OAR1_ADD8 ((uint16_t)0x0100) |
| #define | I2C_OAR1_ADD9 ((uint16_t)0x0200) |
| #define | I2C_OAR1_ADDMODE ((uint16_t)0x8000) |
| #define | I2C_OAR2_ENDUAL ((uint8_t)0x01) |
| #define | I2C_OAR2_ADD2 ((uint8_t)0xFE) |
| #define | I2C_DR_DR ((uint8_t)0xFF) |
| #define | I2C_SR1_SB ((uint16_t)0x0001) |
| #define | I2C_SR1_ADDR ((uint16_t)0x0002) |
| #define | I2C_SR1_BTF ((uint16_t)0x0004) |
| #define | I2C_SR1_ADD10 ((uint16_t)0x0008) |
| #define | I2C_SR1_STOPF ((uint16_t)0x0010) |
| #define | I2C_SR1_RXNE ((uint16_t)0x0040) |
| #define | I2C_SR1_TXE ((uint16_t)0x0080) |
| #define | I2C_SR1_BERR ((uint16_t)0x0100) |
| #define | I2C_SR1_ARLO ((uint16_t)0x0200) |
| #define | I2C_SR1_AF ((uint16_t)0x0400) |
| #define | I2C_SR1_OVR ((uint16_t)0x0800) |
| #define | I2C_SR1_PECERR ((uint16_t)0x1000) |
| #define | I2C_SR1_TIMEOUT ((uint16_t)0x4000) |
| #define | I2C_SR1_SMBALERT ((uint16_t)0x8000) |
| #define | I2C_SR2_MSL ((uint16_t)0x0001) |
| #define | I2C_SR2_BUSY ((uint16_t)0x0002) |
| #define | I2C_SR2_TRA ((uint16_t)0x0004) |
| #define | I2C_SR2_GENCALL ((uint16_t)0x0010) |
| #define | I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) |
| #define | I2C_SR2_SMBHOST ((uint16_t)0x0040) |
| #define | I2C_SR2_DUALF ((uint16_t)0x0080) |
| #define | I2C_SR2_PEC ((uint16_t)0xFF00) |
| #define | I2C_CCR_CCR ((uint16_t)0x0FFF) |
| #define | I2C_CCR_DUTY ((uint16_t)0x4000) |
| #define | I2C_CCR_FS ((uint16_t)0x8000) |
| #define | I2C_TRISE_TRISE ((uint8_t)0x3F) |
| #define | I2C_FLTR_DNF ((uint8_t)0x0F) |
| #define | I2C_FLTR_ANOFF ((uint8_t)0x10) |
| #define | IWDG_KR_KEY ((uint16_t)0xFFFF) |
| #define | IWDG_PR_PR ((uint8_t)0x07) |
| #define | IWDG_PR_PR_0 ((uint8_t)0x01) |
| #define | IWDG_PR_PR_1 ((uint8_t)0x02) |
| #define | IWDG_PR_PR_2 ((uint8_t)0x04) |
| #define | IWDG_RLR_RL ((uint16_t)0x0FFF) |
| #define | IWDG_SR_PVU ((uint8_t)0x01) |
| #define | IWDG_SR_RVU ((uint8_t)0x02) |
| #define | LTDC_SSCR_VSH ((uint32_t)0x000007FF) |
| #define | LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) |
| #define | LTDC_BPCR_AVBP ((uint32_t)0x000007FF) |
| #define | LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) |
| #define | LTDC_AWCR_AAH ((uint32_t)0x000007FF) |
| #define | LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) |
| #define | LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) |
| #define | LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) |
| #define | LTDC_GCR_LTDCEN ((uint32_t)0x00000001) |
| #define | LTDC_GCR_DBW ((uint32_t)0x00000070) |
| #define | LTDC_GCR_DGW ((uint32_t)0x00000700) |
| #define | LTDC_GCR_DRW ((uint32_t)0x00007000) |
| #define | LTDC_GCR_DEN ((uint32_t)0x00010000) |
| #define | LTDC_GCR_PCPOL ((uint32_t)0x10000000) |
| #define | LTDC_GCR_DEPOL ((uint32_t)0x20000000) |
| #define | LTDC_GCR_VSPOL ((uint32_t)0x40000000) |
| #define | LTDC_GCR_HSPOL ((uint32_t)0x80000000) |
| #define | LTDC_GCR_DTEN LTDC_GCR_DEN |
| #define | LTDC_SRCR_IMR ((uint32_t)0x00000001) |
| #define | LTDC_SRCR_VBR ((uint32_t)0x00000002) |
| #define | LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) |
| #define | LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) |
| #define | LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) |
| #define | LTDC_IER_LIE ((uint32_t)0x00000001) |
| #define | LTDC_IER_FUIE ((uint32_t)0x00000002) |
| #define | LTDC_IER_TERRIE ((uint32_t)0x00000004) |
| #define | LTDC_IER_RRIE ((uint32_t)0x00000008) |
| #define | LTDC_ISR_LIF ((uint32_t)0x00000001) |
| #define | LTDC_ISR_FUIF ((uint32_t)0x00000002) |
| #define | LTDC_ISR_TERRIF ((uint32_t)0x00000004) |
| #define | LTDC_ISR_RRIF ((uint32_t)0x00000008) |
| #define | LTDC_ICR_CLIF ((uint32_t)0x00000001) |
| #define | LTDC_ICR_CFUIF ((uint32_t)0x00000002) |
| #define | LTDC_ICR_CTERRIF ((uint32_t)0x00000004) |
| #define | LTDC_ICR_CRRIF ((uint32_t)0x00000008) |
| #define | LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) |
| #define | LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) |
| #define | LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) |
| #define | LTDC_CDSR_VDES ((uint32_t)0x00000001) |
| #define | LTDC_CDSR_HDES ((uint32_t)0x00000002) |
| #define | LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) |
| #define | LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) |
| #define | LTDC_LxCR_LEN ((uint32_t)0x00000001) |
| #define | LTDC_LxCR_COLKEN ((uint32_t)0x00000002) |
| #define | LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) |
| #define | LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) |
| #define | LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) |
| #define | LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) |
| #define | LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) |
| #define | LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) |
| #define | LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) |
| #define | LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) |
| #define | LTDC_LxPFCR_PF ((uint32_t)0x00000007) |
| #define | LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) |
| #define | LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) |
| #define | LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) |
| #define | LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) |
| #define | LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) |
| #define | LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) |
| #define | LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) |
| #define | LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) |
| #define | LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) |
| #define | LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) |
| #define | LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) |
| #define | LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) |
| #define | LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) |
| #define | LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) |
| #define | LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CR_FPDS ((uint32_t)0x00000200) |
| #define | PWR_CR_LPUDS ((uint32_t)0x00000400) |
| #define | PWR_CR_MRUDS ((uint32_t)0x00000800) |
| #define | PWR_CR_LPLVDS ((uint32_t)0x00000400) |
| #define | PWR_CR_MRLVDS ((uint32_t)0x00000800) |
| #define | PWR_CR_ADCDC1 ((uint32_t)0x00002000) |
| #define | PWR_CR_VOS ((uint32_t)0x0000C000) |
| #define | PWR_CR_VOS_0 ((uint32_t)0x00004000) |
| #define | PWR_CR_VOS_1 ((uint32_t)0x00008000) |
| #define | PWR_CR_ODEN ((uint32_t)0x00010000) |
| #define | PWR_CR_ODSWEN ((uint32_t)0x00020000) |
| #define | PWR_CR_UDEN ((uint32_t)0x000C0000) |
| #define | PWR_CR_UDEN_0 ((uint32_t)0x00040000) |
| #define | PWR_CR_UDEN_1 ((uint32_t)0x00080000) |
| #define | PWR_CR_FMSSR ((uint32_t)0x00100000) |
| #define | PWR_CR_FISSR ((uint32_t)0x00200000) |
| #define | PWR_CR_PMODE PWR_CR_VOS |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_BRR ((uint32_t)0x00000008) |
| #define | PWR_CSR_WUPP ((uint32_t)0x00000080) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | PWR_CSR_BRE ((uint32_t)0x00000200) |
| #define | PWR_CSR_VOSRDY ((uint32_t)0x00004000) |
| #define | PWR_CSR_ODRDY ((uint32_t)0x00010000) |
| #define | PWR_CSR_ODSWRDY ((uint32_t)0x00020000) |
| #define | PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) |
| #define | PWR_CSR_REGRDY PWR_CSR_VOSRDY |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSITRIM_0 ((uint32_t)0x00000008 |
| #define | RCC_CR_HSITRIM_1 ((uint32_t)0x00000010 |
| #define | RCC_CR_HSITRIM_2 ((uint32_t)0x00000020 |
| #define | RCC_CR_HSITRIM_3 ((uint32_t)0x00000040 |
| #define | RCC_CR_HSITRIM_4 ((uint32_t)0x00000080 |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSICAL_0 ((uint32_t)0x00000100 |
| #define | RCC_CR_HSICAL_1 ((uint32_t)0x00000200 |
| #define | RCC_CR_HSICAL_2 ((uint32_t)0x00000400 |
| #define | RCC_CR_HSICAL_3 ((uint32_t)0x00000800 |
| #define | RCC_CR_HSICAL_4 ((uint32_t)0x00001000 |
| #define | RCC_CR_HSICAL_5 ((uint32_t)0x00002000 |
| #define | RCC_CR_HSICAL_6 ((uint32_t)0x00004000 |
| #define | RCC_CR_HSICAL_7 ((uint32_t)0x00008000 |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CR_PLLI2SON ((uint32_t)0x04000000) |
| #define | RCC_CR_PLLI2SRDY ((uint32_t)0x08000000) |
| #define | RCC_CR_PLLSAION ((uint32_t)0x10000000) |
| #define | RCC_CR_PLLSAIRDY ((uint32_t)0x20000000) |
| #define | RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F) |
| #define | RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001) |
| #define | RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002) |
| #define | RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004) |
| #define | RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008) |
| #define | RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010) |
| #define | RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020) |
| #define | RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0) |
| #define | RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040) |
| #define | RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080) |
| #define | RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100) |
| #define | RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200) |
| #define | RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400) |
| #define | RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800) |
| #define | RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000) |
| #define | RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000) |
| #define | RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000) |
| #define | RCC_PLLCFGR_PLLP ((uint32_t)0x00030000) |
| #define | RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000) |
| #define | RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000) |
| #define | RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000) |
| #define | RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000) |
| #define | RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000) |
| #define | RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000) |
| #define | RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000) |
| #define | RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000) |
| #define | RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000) |
| #define | RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) |
| #define | RCC_CFGR_RTCPRE ((uint32_t)0x001F0000) |
| #define | RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000) |
| #define | RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_MCO1 ((uint32_t)0x00600000) |
| #define | RCC_CFGR_MCO1_0 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_MCO1_1 ((uint32_t)0x00400000) |
| #define | RCC_CFGR_I2SSRC ((uint32_t)0x00800000) |
| #define | RCC_CFGR_MCO1PRE ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO2PRE ((uint32_t)0x38000000) |
| #define | RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000) |
| #define | RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000) |
| #define | RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000) |
| #define | RCC_CFGR_MCO2 ((uint32_t)0xC0000000) |
| #define | RCC_CFGR_MCO2_0 ((uint32_t)0x40000000) |
| #define | RCC_CFGR_MCO2_1 ((uint32_t)0x80000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020) |
| #define | RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000) |
| #define | RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000) |
| #define | RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001) |
| #define | RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002) |
| #define | RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004) |
| #define | RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008) |
| #define | RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010) |
| #define | RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020) |
| #define | RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040) |
| #define | RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080) |
| #define | RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100) |
| #define | RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200) |
| #define | RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400) |
| #define | RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000) |
| #define | RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000) |
| #define | RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) |
| #define | RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000) |
| #define | RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) |
| #define | RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000) |
| #define | RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) |
| #define | RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010) |
| #define | RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020) |
| #define | RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST |
| #define | RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) |
| #define | RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) |
| #define | RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) |
| #define | RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
| #define | RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000) |
| #define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
| #define | RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000) |
| #define | RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_UART9RST ((uint32_t)0x00000040) |
| #define | RCC_APB2RSTR_UART10RST ((uint32_t)0x00000080) |
| #define | RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100) |
| #define | RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000) |
| #define | RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000) |
| #define | RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000) |
| #define | RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000) |
| #define | RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000) |
| #define | RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000) |
| #define | RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000) |
| #define | RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000) |
| #define | RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST |
| #define | RCC_APB2RSTR_DFSDMRST RCC_APB2RSTR_DFSDM1RST |
| #define | RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001) |
| #define | RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002) |
| #define | RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004) |
| #define | RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008) |
| #define | RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010) |
| #define | RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020) |
| #define | RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040) |
| #define | RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080) |
| #define | RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100) |
| #define | RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200) |
| #define | RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400) |
| #define | RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000) |
| #define | RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000) |
| #define | RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000) |
| #define | RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000) |
| #define | RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000) |
| #define | RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000) |
| #define | RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000) |
| #define | RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000) |
| #define | RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000) |
| #define | RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000) |
| #define | RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000) |
| #define | RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000) |
| #define | RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001) |
| #define | RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010) |
| #define | RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020) |
| #define | RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040) |
| #define | RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) |
| #define | RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) |
| #define | RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
| #define | RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000) |
| #define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
| #define | RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_APB1ENR_UART7EN ((uint32_t)0x40000000) |
| #define | RCC_APB1ENR_UART8EN ((uint32_t)0x80000000) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_UART9EN ((uint32_t)0x00000040) |
| #define | RCC_APB2ENR_UART10EN ((uint32_t)0x00000080) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100) |
| #define | RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400) |
| #define | RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000) |
| #define | RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_EXTIEN ((uint32_t)0x00008000) |
| #define | RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000) |
| #define | RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000) |
| #define | RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000) |
| #define | RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000) |
| #define | RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000) |
| #define | RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000) |
| #define | RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000) |
| #define | RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001) |
| #define | RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002) |
| #define | RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004) |
| #define | RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008) |
| #define | RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010) |
| #define | RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020) |
| #define | RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040) |
| #define | RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080) |
| #define | RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100) |
| #define | RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200) |
| #define | RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400) |
| #define | RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000) |
| #define | RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000) |
| #define | RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000) |
| #define | RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000) |
| #define | RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000) |
| #define | RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000) |
| #define | RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000) |
| #define | RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000) |
| #define | RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000) |
| #define | RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000) |
| #define | RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000) |
| #define | RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000) |
| #define | RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000) |
| #define | RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000) |
| #define | RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000) |
| #define | RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001) |
| #define | RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010) |
| #define | RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020) |
| #define | RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040) |
| #define | RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080) |
| #define | RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) |
| #define | RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) |
| #define | RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) |
| #define | RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) |
| #define | RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) |
| #define | RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) |
| #define | RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040) |
| #define | RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080) |
| #define | RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100) |
| #define | RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) |
| #define | RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) |
| #define | RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) |
| #define | RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) |
| #define | RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) |
| #define | RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) |
| #define | RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) |
| #define | RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) |
| #define | RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) |
| #define | RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000) |
| #define | RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000) |
| #define | RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000) |
| #define | RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) |
| #define | RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) |
| #define | RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000) |
| #define | RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000) |
| #define | RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001) |
| #define | RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002) |
| #define | RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010) |
| #define | RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020) |
| #define | RCC_APB2LPENR_UART9LPEN ((uint32_t)0x00000040) |
| #define | RCC_APB2LPENR_UART10LPEN ((uint32_t)0x00000080) |
| #define | RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100) |
| #define | RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200) |
| #define | RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400) |
| #define | RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) |
| #define | RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) |
| #define | RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000) |
| #define | RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000) |
| #define | RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000) |
| #define | RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000) |
| #define | RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000) |
| #define | RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000) |
| #define | RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000) |
| #define | RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000) |
| #define | RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_LSEMOD ((uint32_t)0x00000008) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_BORRSTF ((uint32_t)0x02000000) |
| #define | RCC_CSR_PADRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_WDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | RCC_SSCGR_MODPER ((uint32_t)0x00001FFF) |
| #define | RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000) |
| #define | RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000) |
| #define | RCC_SSCGR_SSCGEN ((uint32_t)0x80000000) |
| #define | RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F) |
| #define | RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001) |
| #define | RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002) |
| #define | RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004) |
| #define | RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008) |
| #define | RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010) |
| #define | RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020) |
| #define | RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0) |
| #define | RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040) |
| #define | RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080) |
| #define | RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100) |
| #define | RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200) |
| #define | RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400) |
| #define | RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800) |
| #define | RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000) |
| #define | RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000) |
| #define | RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000) |
| #define | RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000) |
| #define | RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000) |
| #define | RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000) |
| #define | RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000) |
| #define | RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000) |
| #define | RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000) |
| #define | RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000) |
| #define | RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000) |
| #define | RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000) |
| #define | RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0) |
| #define | RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040) |
| #define | RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080) |
| #define | RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100) |
| #define | RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200) |
| #define | RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400) |
| #define | RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800) |
| #define | RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000) |
| #define | RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000) |
| #define | RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000) |
| #define | RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000) |
| #define | RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000) |
| #define | RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000) |
| #define | RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000) |
| #define | RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000) |
| #define | RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000) |
| #define | RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000) |
| #define | RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000) |
| #define | RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000) |
| #define | RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F) |
| #define | RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00) |
| #define | RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000) |
| #define | RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000) |
| #define | RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000) |
| #define | RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000) |
| #define | RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000) |
| #define | RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000) |
| #define | RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000) |
| #define | RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000) |
| #define | RNG_CR_RNGEN ((uint32_t)0x00000004) |
| #define | RNG_CR_IE ((uint32_t)0x00000008) |
| #define | RNG_SR_DRDY ((uint32_t)0x00000001) |
| #define | RNG_SR_CECS ((uint32_t)0x00000002) |
| #define | RNG_SR_SECS ((uint32_t)0x00000004) |
| #define | RNG_SR_CEIS ((uint32_t)0x00000020) |
| #define | RNG_SR_SEIS ((uint32_t)0x00000040) |
| #define | RTC_TR_PM ((uint32_t)0x00400000) |
| #define | RTC_TR_HT ((uint32_t)0x00300000) |
| #define | RTC_TR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TR_ST ((uint32_t)0x00000070) |
| #define | RTC_TR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_DR_YT ((uint32_t)0x00F00000) |
| #define | RTC_DR_YT_0 ((uint32_t)0x00100000) |
| #define | RTC_DR_YT_1 ((uint32_t)0x00200000) |
| #define | RTC_DR_YT_2 ((uint32_t)0x00400000) |
| #define | RTC_DR_YT_3 ((uint32_t)0x00800000) |
| #define | RTC_DR_YU ((uint32_t)0x000F0000) |
| #define | RTC_DR_YU_0 ((uint32_t)0x00010000) |
| #define | RTC_DR_YU_1 ((uint32_t)0x00020000) |
| #define | RTC_DR_YU_2 ((uint32_t)0x00040000) |
| #define | RTC_DR_YU_3 ((uint32_t)0x00080000) |
| #define | RTC_DR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_DR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_DR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_DR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_DR_MT ((uint32_t)0x00001000) |
| #define | RTC_DR_MU ((uint32_t)0x00000F00) |
| #define | RTC_DR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_DR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_DR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_DR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_DR_DT ((uint32_t)0x00000030) |
| #define | RTC_DR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_DR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_DR_DU ((uint32_t)0x0000000F) |
| #define | RTC_DR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_DR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_DR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_DR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_CR_COE ((uint32_t)0x00800000) |
| #define | RTC_CR_OSEL ((uint32_t)0x00600000) |
| #define | RTC_CR_OSEL_0 ((uint32_t)0x00200000) |
| #define | RTC_CR_OSEL_1 ((uint32_t)0x00400000) |
| #define | RTC_CR_POL ((uint32_t)0x00100000) |
| #define | RTC_CR_COSEL ((uint32_t)0x00080000) |
| #define | RTC_CR_BCK ((uint32_t)0x00040000) |
| #define | RTC_CR_SUB1H ((uint32_t)0x00020000) |
| #define | RTC_CR_ADD1H ((uint32_t)0x00010000) |
| #define | RTC_CR_TSIE ((uint32_t)0x00008000) |
| #define | RTC_CR_WUTIE ((uint32_t)0x00004000) |
| #define | RTC_CR_ALRBIE ((uint32_t)0x00002000) |
| #define | RTC_CR_ALRAIE ((uint32_t)0x00001000) |
| #define | RTC_CR_TSE ((uint32_t)0x00000800) |
| #define | RTC_CR_WUTE ((uint32_t)0x00000400) |
| #define | RTC_CR_ALRBE ((uint32_t)0x00000200) |
| #define | RTC_CR_ALRAE ((uint32_t)0x00000100) |
| #define | RTC_CR_DCE ((uint32_t)0x00000080) |
| #define | RTC_CR_FMT ((uint32_t)0x00000040) |
| #define | RTC_CR_BYPSHAD ((uint32_t)0x00000020) |
| #define | RTC_CR_REFCKON ((uint32_t)0x00000010) |
| #define | RTC_CR_TSEDGE ((uint32_t)0x00000008) |
| #define | RTC_CR_WUCKSEL ((uint32_t)0x00000007) |
| #define | RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) |
| #define | RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) |
| #define | RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) |
| #define | RTC_ISR_RECALPF ((uint32_t)0x00010000) |
| #define | RTC_ISR_TAMP1F ((uint32_t)0x00002000) |
| #define | RTC_ISR_TAMP2F ((uint32_t)0x00004000) |
| #define | RTC_ISR_TSOVF ((uint32_t)0x00001000) |
| #define | RTC_ISR_TSF ((uint32_t)0x00000800) |
| #define | RTC_ISR_WUTF ((uint32_t)0x00000400) |
| #define | RTC_ISR_ALRBF ((uint32_t)0x00000200) |
| #define | RTC_ISR_ALRAF ((uint32_t)0x00000100) |
| #define | RTC_ISR_INIT ((uint32_t)0x00000080) |
| #define | RTC_ISR_INITF ((uint32_t)0x00000040) |
| #define | RTC_ISR_RSF ((uint32_t)0x00000020) |
| #define | RTC_ISR_INITS ((uint32_t)0x00000010) |
| #define | RTC_ISR_SHPF ((uint32_t)0x00000008) |
| #define | RTC_ISR_WUTWF ((uint32_t)0x00000004) |
| #define | RTC_ISR_ALRBWF ((uint32_t)0x00000002) |
| #define | RTC_ISR_ALRAWF ((uint32_t)0x00000001) |
| #define | RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) |
| #define | RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF) |
| #define | RTC_WUTR_WUT ((uint32_t)0x0000FFFF) |
| #define | RTC_CALIBR_DCS ((uint32_t)0x00000080) |
| #define | RTC_CALIBR_DC ((uint32_t)0x0000001F) |
| #define | RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMAR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMAR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMAR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMAR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMAR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMAR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMAR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMAR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMAR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMBR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMBR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMBR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMBR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMBR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMBR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMBR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMBR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMBR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_WPR_KEY ((uint32_t)0x000000FF) |
| #define | RTC_SSR_SS ((uint32_t)0x0000FFFF) |
| #define | RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) |
| #define | RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) |
| #define | RTC_TSTR_PM ((uint32_t)0x00400000) |
| #define | RTC_TSTR_HT ((uint32_t)0x00300000) |
| #define | RTC_TSTR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TSTR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TSTR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TSTR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TSTR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TSTR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TSTR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TSTR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TSTR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TSTR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TSTR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TSTR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TSTR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSTR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSTR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSTR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSTR_ST ((uint32_t)0x00000070) |
| #define | RTC_TSTR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TSTR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TSTR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TSTR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TSTR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSTR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSTR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSTR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSDR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_TSDR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_TSDR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_TSDR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_TSDR_MT ((uint32_t)0x00001000) |
| #define | RTC_TSDR_MU ((uint32_t)0x00000F00) |
| #define | RTC_TSDR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSDR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSDR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSDR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSDR_DT ((uint32_t)0x00000030) |
| #define | RTC_TSDR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_TSDR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_TSDR_DU ((uint32_t)0x0000000F) |
| #define | RTC_TSDR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSDR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSDR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSDR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSSSR_SS ((uint32_t)0x0000FFFF) |
| #define | RTC_CALR_CALP ((uint32_t)0x00008000) |
| #define | RTC_CALR_CALW8 ((uint32_t)0x00004000) |
| #define | RTC_CALR_CALW16 ((uint32_t)0x00002000) |
| #define | RTC_CALR_CALM ((uint32_t)0x000001FF) |
| #define | RTC_CALR_CALM_0 ((uint32_t)0x00000001) |
| #define | RTC_CALR_CALM_1 ((uint32_t)0x00000002) |
| #define | RTC_CALR_CALM_2 ((uint32_t)0x00000004) |
| #define | RTC_CALR_CALM_3 ((uint32_t)0x00000008) |
| #define | RTC_CALR_CALM_4 ((uint32_t)0x00000010) |
| #define | RTC_CALR_CALM_5 ((uint32_t)0x00000020) |
| #define | RTC_CALR_CALM_6 ((uint32_t)0x00000040) |
| #define | RTC_CALR_CALM_7 ((uint32_t)0x00000080) |
| #define | RTC_CALR_CALM_8 ((uint32_t)0x00000100) |
| #define | RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) |
| #define | RTC_TAFCR_TSINSEL ((uint32_t)0x00020000) |
| #define | RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000) |
| #define | RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) |
| #define | RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) |
| #define | RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) |
| #define | RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) |
| #define | RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) |
| #define | RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) |
| #define | RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) |
| #define | RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) |
| #define | RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) |
| #define | RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) |
| #define | RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) |
| #define | RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) |
| #define | RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010) |
| #define | RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) |
| #define | RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) |
| #define | RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) |
| #define | RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) |
| #define | RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) |
| #define | RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) |
| #define | RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) |
| #define | RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) |
| #define | RTC_BKP0R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP1R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP2R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP3R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP4R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP5R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP6R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP7R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP8R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP9R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP10R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP11R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP12R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP13R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP14R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP15R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP16R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP17R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP18R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP19R ((uint32_t)0xFFFFFFFF) |
| #define | SAI_GCR_SYNCIN ((uint32_t)0x00000003) |
| #define | SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) |
| #define | SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) |
| #define | SAI_GCR_SYNCOUT ((uint32_t)0x00000030) |
| #define | SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) |
| #define | SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) |
| #define | SAI_xCR1_MODE ((uint32_t)0x00000003) |
| #define | SAI_xCR1_MODE_0 ((uint32_t)0x00000001) |
| #define | SAI_xCR1_MODE_1 ((uint32_t)0x00000002) |
| #define | SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) |
| #define | SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) |
| #define | SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) |
| #define | SAI_xCR1_DS ((uint32_t)0x000000E0) |
| #define | SAI_xCR1_DS_0 ((uint32_t)0x00000020) |
| #define | SAI_xCR1_DS_1 ((uint32_t)0x00000040) |
| #define | SAI_xCR1_DS_2 ((uint32_t)0x00000080) |
| #define | SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) |
| #define | SAI_xCR1_CKSTR ((uint32_t)0x00000200) |
| #define | SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) |
| #define | SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) |
| #define | SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) |
| #define | SAI_xCR1_MONO ((uint32_t)0x00001000) |
| #define | SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) |
| #define | SAI_xCR1_SAIEN ((uint32_t)0x00010000) |
| #define | SAI_xCR1_DMAEN ((uint32_t)0x00020000) |
| #define | SAI_xCR1_NODIV ((uint32_t)0x00080000) |
| #define | SAI_xCR1_MCKDIV ((uint32_t)0x00780000) |
| #define | SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) |
| #define | SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) |
| #define | SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) |
| #define | SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) |
| #define | SAI_xCR2_FTH ((uint32_t)0x00000003) |
| #define | SAI_xCR2_FTH_0 ((uint32_t)0x00000001) |
| #define | SAI_xCR2_FTH_1 ((uint32_t)0x00000002) |
| #define | SAI_xCR2_FFLUSH ((uint32_t)0x00000008) |
| #define | SAI_xCR2_TRIS ((uint32_t)0x00000010) |
| #define | SAI_xCR2_MUTE ((uint32_t)0x00000020) |
| #define | SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) |
| #define | SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) |
| #define | SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) |
| #define | SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) |
| #define | SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) |
| #define | SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) |
| #define | SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) |
| #define | SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) |
| #define | SAI_xCR2_CPL ((uint32_t)0x00002000) |
| #define | SAI_xCR2_COMP ((uint32_t)0x0000C000) |
| #define | SAI_xCR2_COMP_0 ((uint32_t)0x00004000) |
| #define | SAI_xCR2_COMP_1 ((uint32_t)0x00008000) |
| #define | SAI_xFRCR_FRL ((uint32_t)0x000000FF) |
| #define | SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) |
| #define | SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) |
| #define | SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) |
| #define | SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) |
| #define | SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) |
| #define | SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) |
| #define | SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) |
| #define | SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) |
| #define | SAI_xFRCR_FSALL ((uint32_t)0x00007F00) |
| #define | SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) |
| #define | SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) |
| #define | SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) |
| #define | SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) |
| #define | SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) |
| #define | SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) |
| #define | SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) |
| #define | SAI_xFRCR_FSDEF ((uint32_t)0x00010000) |
| #define | SAI_xFRCR_FSPOL ((uint32_t)0x00020000) |
| #define | SAI_xFRCR_FSOFF ((uint32_t)0x00040000) |
| #define | SAI_xFRCR_FSPO SAI_xFRCR_FSPOL |
| #define | SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) |
| #define | SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) |
| #define | SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) |
| #define | SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) |
| #define | SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) |
| #define | SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) |
| #define | SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) |
| #define | SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) |
| #define | SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) |
| #define | SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) |
| #define | SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) |
| #define | SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) |
| #define | SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) |
| #define | SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) |
| #define | SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) |
| #define | SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) |
| #define | SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) |
| #define | SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) |
| #define | SAI_xIMR_FREQIE ((uint32_t)0x00000008) |
| #define | SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) |
| #define | SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) |
| #define | SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) |
| #define | SAI_xSR_OVRUDR ((uint32_t)0x00000001) |
| #define | SAI_xSR_MUTEDET ((uint32_t)0x00000002) |
| #define | SAI_xSR_WCKCFG ((uint32_t)0x00000004) |
| #define | SAI_xSR_FREQ ((uint32_t)0x00000008) |
| #define | SAI_xSR_CNRDY ((uint32_t)0x00000010) |
| #define | SAI_xSR_AFSDET ((uint32_t)0x00000020) |
| #define | SAI_xSR_LFSDET ((uint32_t)0x00000040) |
| #define | SAI_xSR_FLVL ((uint32_t)0x00070000) |
| #define | SAI_xSR_FLVL_0 ((uint32_t)0x00010000) |
| #define | SAI_xSR_FLVL_1 ((uint32_t)0x00020000) |
| #define | SAI_xSR_FLVL_2 ((uint32_t)0x00030000) |
| #define | SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) |
| #define | SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) |
| #define | SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) |
| #define | SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) |
| #define | SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) |
| #define | SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) |
| #define | SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) |
| #define | SAI_xDR_DATA ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_POWER_PWRCTRL ((uint8_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint16_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint16_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint16_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint16_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint16_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint16_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint16_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint16_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint16_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint16_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint16_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint16_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint16_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint16_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint16_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | SPI_CR1_CPHA ((uint16_t)0x0001) |
| #define | SPI_CR1_CPOL ((uint16_t)0x0002) |
| #define | SPI_CR1_MSTR ((uint16_t)0x0004) |
| #define | SPI_CR1_BR ((uint16_t)0x0038) |
| #define | SPI_CR1_BR_0 ((uint16_t)0x0008) |
| #define | SPI_CR1_BR_1 ((uint16_t)0x0010) |
| #define | SPI_CR1_BR_2 ((uint16_t)0x0020) |
| #define | SPI_CR1_SPE ((uint16_t)0x0040) |
| #define | SPI_CR1_LSBFIRST ((uint16_t)0x0080) |
| #define | SPI_CR1_SSI ((uint16_t)0x0100) |
| #define | SPI_CR1_SSM ((uint16_t)0x0200) |
| #define | SPI_CR1_RXONLY ((uint16_t)0x0400) |
| #define | SPI_CR1_DFF ((uint16_t)0x0800) |
| #define | SPI_CR1_CRCNEXT ((uint16_t)0x1000) |
| #define | SPI_CR1_CRCEN ((uint16_t)0x2000) |
| #define | SPI_CR1_BIDIOE ((uint16_t)0x4000) |
| #define | SPI_CR1_BIDIMODE ((uint16_t)0x8000) |
| #define | SPI_CR2_RXDMAEN ((uint8_t)0x01) |
| #define | SPI_CR2_TXDMAEN ((uint8_t)0x02) |
| #define | SPI_CR2_SSOE ((uint8_t)0x04) |
| #define | SPI_CR2_ERRIE ((uint8_t)0x20) |
| #define | SPI_CR2_RXNEIE ((uint8_t)0x40) |
| #define | SPI_CR2_TXEIE ((uint8_t)0x80) |
| #define | SPI_SR_RXNE ((uint8_t)0x01) |
| #define | SPI_SR_TXE ((uint8_t)0x02) |
| #define | SPI_SR_CHSIDE ((uint8_t)0x04) |
| #define | SPI_SR_UDR ((uint8_t)0x08) |
| #define | SPI_SR_CRCERR ((uint8_t)0x10) |
| #define | SPI_SR_MODF ((uint8_t)0x20) |
| #define | SPI_SR_OVR ((uint8_t)0x40) |
| #define | SPI_SR_BSY ((uint8_t)0x80) |
| #define | SPI_DR_DR ((uint16_t)0xFFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) |
| #define | SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) |
| #define | SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) |
| #define | SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) |
| #define | SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) |
| #define | SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) |
| #define | SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) |
| #define | SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) |
| #define | SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) |
| #define | SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) |
| #define | SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) |
| #define | SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) |
| #define | SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) |
| #define | SPI_I2SCFGR_I2SE ((uint16_t)0x0400) |
| #define | SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) |
| #define | SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) |
| #define | SPI_I2SPR_ODD ((uint16_t)0x0100) |
| #define | SPI_I2SPR_MCKOE ((uint16_t)0x0200) |
| #define | SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) |
| #define | SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) |
| #define | SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) |
| #define | SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004) |
| #define | SYSCFG_MEMRMP_FB_MODE ((uint32_t)0x00000100) |
| #define | SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) |
| #define | SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400) |
| #define | SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800) |
| #define | SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) |
| #define | SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) |
| #define | SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) |
| #define | SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) |
| #define | SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) |
| #define | SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL |
| #define | SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) |
| EXTI0 configuration | |
| #define | SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR1_EXTI0_PJ ((uint16_t)0x0009) |
| #define | SYSCFG_EXTICR1_EXTI0_PK ((uint16_t)0x000A) |
| #define | SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) |
| EXTI1 configuration | |
| #define | SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) |
| #define | SYSCFG_EXTICR1_EXTI1_PJ ((uint16_t)0x0090) |
| #define | SYSCFG_EXTICR1_EXTI1_PK ((uint16_t)0x00A0) |
| #define | SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) |
| EXTI2 configuration | |
| #define | SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) |
| #define | SYSCFG_EXTICR1_EXTI2_PJ ((uint16_t)0x0900) |
| #define | SYSCFG_EXTICR1_EXTI2_PK ((uint16_t)0x0A00) |
| #define | SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) |
| EXTI3 configuration | |
| #define | SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) |
| #define | SYSCFG_EXTICR1_EXTI3_PJ ((uint16_t)0x9000) |
| #define | SYSCFG_EXTICR1_EXTI3_PK ((uint16_t)0xA000) |
| #define | SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) |
| EXTI4 configuration | |
| #define | SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR2_EXTI4_PJ ((uint16_t)0x0009) |
| #define | SYSCFG_EXTICR2_EXTI4_PK ((uint16_t)0x000A) |
| #define | SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) |
| EXTI5 configuration | |
| #define | SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) |
| #define | SYSCFG_EXTICR2_EXTI5_PJ ((uint16_t)0x0090) |
| #define | SYSCFG_EXTICR2_EXTI5_PK ((uint16_t)0x00A0) |
| #define | SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) |
| EXTI6 configuration | |
| #define | SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) |
| #define | SYSCFG_EXTICR2_EXTI6_PJ ((uint16_t)0x0900) |
| #define | SYSCFG_EXTICR2_EXTI6_PK ((uint16_t)0x0A00) |
| #define | SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) |
| EXTI7 configuration | |
| #define | SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) |
| #define | SYSCFG_EXTICR2_EXTI7_PJ ((uint16_t)0x9000) |
| #define | SYSCFG_EXTICR2_EXTI7_PK ((uint16_t)0xA000) |
| #define | SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) |
| EXTI8 configuration | |
| #define | SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR3_EXTI8_PJ ((uint16_t)0x0009) |
| #define | SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) |
| EXTI9 configuration | |
| #define | SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) |
| #define | SYSCFG_EXTICR3_EXTI9_PJ ((uint16_t)0x0090) |
| #define | SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) |
| EXTI10 configuration | |
| #define | SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) |
| #define | SYSCFG_EXTICR3_EXTI10_PJ ((uint16_t)0x0900) |
| #define | SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) |
| EXTI11 configuration | |
| #define | SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) |
| #define | SYSCFG_EXTICR3_EXTI11_PJ ((uint16_t)0x9000) |
| #define | SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) |
| EXTI12 configuration | |
| #define | SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR4_EXTI12_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR4_EXTI12_PJ ((uint16_t)0x0009) |
| #define | SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) |
| EXTI13 configuration | |
| #define | SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR4_EXTI13_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR4_EXTI13_PJ ((uint16_t)0x0009) |
| #define | SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) |
| EXTI14 configuration | |
| #define | SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR4_EXTI14_PI ((uint16_t)0x0800) |
| #define | SYSCFG_EXTICR4_EXTI14_PJ ((uint16_t)0x0900) |
| #define | SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) |
| EXTI15 configuration | |
| #define | SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR4_EXTI15_PI ((uint16_t)0x8000) |
| #define | SYSCFG_EXTICR4_EXTI15_PJ ((uint16_t)0x9000) |
| #define | SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) |
| #define | SYSCFG_CMPCR_READY ((uint32_t)0x00000100) |
| #define | TIM_CR1_CEN ((uint16_t)0x0001) |
| #define | TIM_CR1_UDIS ((uint16_t)0x0002) |
| #define | TIM_CR1_URS ((uint16_t)0x0004) |
| #define | TIM_CR1_OPM ((uint16_t)0x0008) |
| #define | TIM_CR1_DIR ((uint16_t)0x0010) |
| #define | TIM_CR1_CMS ((uint16_t)0x0060) |
| #define | TIM_CR1_CMS_0 ((uint16_t)0x0020) |
| #define | TIM_CR1_CMS_1 ((uint16_t)0x0040) |
| #define | TIM_CR1_ARPE ((uint16_t)0x0080) |
| #define | TIM_CR1_CKD ((uint16_t)0x0300) |
| #define | TIM_CR1_CKD_0 ((uint16_t)0x0100) |
| #define | TIM_CR1_CKD_1 ((uint16_t)0x0200) |
| #define | TIM_CR2_CCPC ((uint16_t)0x0001) |
| #define | TIM_CR2_CCUS ((uint16_t)0x0004) |
| #define | TIM_CR2_CCDS ((uint16_t)0x0008) |
| #define | TIM_CR2_MMS ((uint16_t)0x0070) |
| #define | TIM_CR2_MMS_0 ((uint16_t)0x0010) |
| #define | TIM_CR2_MMS_1 ((uint16_t)0x0020) |
| #define | TIM_CR2_MMS_2 ((uint16_t)0x0040) |
| #define | TIM_CR2_TI1S ((uint16_t)0x0080) |
| #define | TIM_CR2_OIS1 ((uint16_t)0x0100) |
| #define | TIM_CR2_OIS1N ((uint16_t)0x0200) |
| #define | TIM_CR2_OIS2 ((uint16_t)0x0400) |
| #define | TIM_CR2_OIS2N ((uint16_t)0x0800) |
| #define | TIM_CR2_OIS3 ((uint16_t)0x1000) |
| #define | TIM_CR2_OIS3N ((uint16_t)0x2000) |
| #define | TIM_CR2_OIS4 ((uint16_t)0x4000) |
| #define | TIM_SMCR_SMS ((uint16_t)0x0007) |
| #define | TIM_SMCR_SMS_0 ((uint16_t)0x0001) |
| #define | TIM_SMCR_SMS_1 ((uint16_t)0x0002) |
| #define | TIM_SMCR_SMS_2 ((uint16_t)0x0004) |
| #define | TIM_SMCR_TS ((uint16_t)0x0070) |
| #define | TIM_SMCR_TS_0 ((uint16_t)0x0010) |
| #define | TIM_SMCR_TS_1 ((uint16_t)0x0020) |
| #define | TIM_SMCR_TS_2 ((uint16_t)0x0040) |
| #define | TIM_SMCR_MSM ((uint16_t)0x0080) |
| #define | TIM_SMCR_ETF ((uint16_t)0x0F00) |
| #define | TIM_SMCR_ETF_0 ((uint16_t)0x0100) |
| #define | TIM_SMCR_ETF_1 ((uint16_t)0x0200) |
| #define | TIM_SMCR_ETF_2 ((uint16_t)0x0400) |
| #define | TIM_SMCR_ETF_3 ((uint16_t)0x0800) |
| #define | TIM_SMCR_ETPS ((uint16_t)0x3000) |
| #define | TIM_SMCR_ETPS_0 ((uint16_t)0x1000) |
| #define | TIM_SMCR_ETPS_1 ((uint16_t)0x2000) |
| #define | TIM_SMCR_ECE ((uint16_t)0x4000) |
| #define | TIM_SMCR_ETP ((uint16_t)0x8000) |
| #define | TIM_DIER_UIE ((uint16_t)0x0001) |
| #define | TIM_DIER_CC1IE ((uint16_t)0x0002) |
| #define | TIM_DIER_CC2IE ((uint16_t)0x0004) |
| #define | TIM_DIER_CC3IE ((uint16_t)0x0008) |
| #define | TIM_DIER_CC4IE ((uint16_t)0x0010) |
| #define | TIM_DIER_COMIE ((uint16_t)0x0020) |
| #define | TIM_DIER_TIE ((uint16_t)0x0040) |
| #define | TIM_DIER_BIE ((uint16_t)0x0080) |
| #define | TIM_DIER_UDE ((uint16_t)0x0100) |
| #define | TIM_DIER_CC1DE ((uint16_t)0x0200) |
| #define | TIM_DIER_CC2DE ((uint16_t)0x0400) |
| #define | TIM_DIER_CC3DE ((uint16_t)0x0800) |
| #define | TIM_DIER_CC4DE ((uint16_t)0x1000) |
| #define | TIM_DIER_COMDE ((uint16_t)0x2000) |
| #define | TIM_DIER_TDE ((uint16_t)0x4000) |
| #define | TIM_SR_UIF ((uint16_t)0x0001) |
| #define | TIM_SR_CC1IF ((uint16_t)0x0002) |
| #define | TIM_SR_CC2IF ((uint16_t)0x0004) |
| #define | TIM_SR_CC3IF ((uint16_t)0x0008) |
| #define | TIM_SR_CC4IF ((uint16_t)0x0010) |
| #define | TIM_SR_COMIF ((uint16_t)0x0020) |
| #define | TIM_SR_TIF ((uint16_t)0x0040) |
| #define | TIM_SR_BIF ((uint16_t)0x0080) |
| #define | TIM_SR_CC1OF ((uint16_t)0x0200) |
| #define | TIM_SR_CC2OF ((uint16_t)0x0400) |
| #define | TIM_SR_CC3OF ((uint16_t)0x0800) |
| #define | TIM_SR_CC4OF ((uint16_t)0x1000) |
| #define | TIM_EGR_UG ((uint8_t)0x01) |
| #define | TIM_EGR_CC1G ((uint8_t)0x02) |
| #define | TIM_EGR_CC2G ((uint8_t)0x04) |
| #define | TIM_EGR_CC3G ((uint8_t)0x08) |
| #define | TIM_EGR_CC4G ((uint8_t)0x10) |
| #define | TIM_EGR_COMG ((uint8_t)0x20) |
| #define | TIM_EGR_TG ((uint8_t)0x40) |
| #define | TIM_EGR_BG ((uint8_t)0x80) |
| #define | TIM_CCMR1_CC1S ((uint16_t)0x0003) |
| #define | TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR1_OC1FE ((uint16_t)0x0004) |
| #define | TIM_CCMR1_OC1PE ((uint16_t)0x0008) |
| #define | TIM_CCMR1_OC1M ((uint16_t)0x0070) |
| #define | TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_OC1CE ((uint16_t)0x0080) |
| #define | TIM_CCMR1_CC2S ((uint16_t)0x0300) |
| #define | TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR1_OC2FE ((uint16_t)0x0400) |
| #define | TIM_CCMR1_OC2PE ((uint16_t)0x0800) |
| #define | TIM_CCMR1_OC2M ((uint16_t)0x7000) |
| #define | TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_OC2CE ((uint16_t)0x8000) |
| #define | TIM_CCMR1_IC1PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR1_IC1F ((uint16_t)0x00F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR1_IC2F ((uint16_t)0xF000) |
| #define | TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) |
| #define | TIM_CCMR2_CC3S ((uint16_t)0x0003) |
| #define | TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR2_OC3FE ((uint16_t)0x0004) |
| #define | TIM_CCMR2_OC3PE ((uint16_t)0x0008) |
| #define | TIM_CCMR2_OC3M ((uint16_t)0x0070) |
| #define | TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_OC3CE ((uint16_t)0x0080) |
| #define | TIM_CCMR2_CC4S ((uint16_t)0x0300) |
| #define | TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR2_OC4FE ((uint16_t)0x0400) |
| #define | TIM_CCMR2_OC4PE ((uint16_t)0x0800) |
| #define | TIM_CCMR2_OC4M ((uint16_t)0x7000) |
| #define | TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_OC4CE ((uint16_t)0x8000) |
| #define | TIM_CCMR2_IC3PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR2_IC3F ((uint16_t)0x00F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR2_IC4F ((uint16_t)0xF000) |
| #define | TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) |
| #define | TIM_CCER_CC1E ((uint16_t)0x0001) |
| #define | TIM_CCER_CC1P ((uint16_t)0x0002) |
| #define | TIM_CCER_CC1NE ((uint16_t)0x0004) |
| #define | TIM_CCER_CC1NP ((uint16_t)0x0008) |
| #define | TIM_CCER_CC2E ((uint16_t)0x0010) |
| #define | TIM_CCER_CC2P ((uint16_t)0x0020) |
| #define | TIM_CCER_CC2NE ((uint16_t)0x0040) |
| #define | TIM_CCER_CC2NP ((uint16_t)0x0080) |
| #define | TIM_CCER_CC3E ((uint16_t)0x0100) |
| #define | TIM_CCER_CC3P ((uint16_t)0x0200) |
| #define | TIM_CCER_CC3NE ((uint16_t)0x0400) |
| #define | TIM_CCER_CC3NP ((uint16_t)0x0800) |
| #define | TIM_CCER_CC4E ((uint16_t)0x1000) |
| #define | TIM_CCER_CC4P ((uint16_t)0x2000) |
| #define | TIM_CCER_CC4NP ((uint16_t)0x8000) |
| #define | TIM_CNT_CNT ((uint16_t)0xFFFF) |
| #define | TIM_PSC_PSC ((uint16_t)0xFFFF) |
| #define | TIM_ARR_ARR ((uint16_t)0xFFFF) |
| #define | TIM_RCR_REP ((uint8_t)0xFF) |
| #define | TIM_CCR1_CCR1 ((uint16_t)0xFFFF) |
| #define | TIM_CCR2_CCR2 ((uint16_t)0xFFFF) |
| #define | TIM_CCR3_CCR3 ((uint16_t)0xFFFF) |
| #define | TIM_CCR4_CCR4 ((uint16_t)0xFFFF) |
| #define | TIM_BDTR_DTG ((uint16_t)0x00FF) |
| #define | TIM_BDTR_DTG_0 ((uint16_t)0x0001) |
| #define | TIM_BDTR_DTG_1 ((uint16_t)0x0002) |
| #define | TIM_BDTR_DTG_2 ((uint16_t)0x0004) |
| #define | TIM_BDTR_DTG_3 ((uint16_t)0x0008) |
| #define | TIM_BDTR_DTG_4 ((uint16_t)0x0010) |
| #define | TIM_BDTR_DTG_5 ((uint16_t)0x0020) |
| #define | TIM_BDTR_DTG_6 ((uint16_t)0x0040) |
| #define | TIM_BDTR_DTG_7 ((uint16_t)0x0080) |
| #define | TIM_BDTR_LOCK ((uint16_t)0x0300) |
| #define | TIM_BDTR_LOCK_0 ((uint16_t)0x0100) |
| #define | TIM_BDTR_LOCK_1 ((uint16_t)0x0200) |
| #define | TIM_BDTR_OSSI ((uint16_t)0x0400) |
| #define | TIM_BDTR_OSSR ((uint16_t)0x0800) |
| #define | TIM_BDTR_BKE ((uint16_t)0x1000) |
| #define | TIM_BDTR_BKP ((uint16_t)0x2000) |
| #define | TIM_BDTR_AOE ((uint16_t)0x4000) |
| #define | TIM_BDTR_MOE ((uint16_t)0x8000) |
| #define | TIM_DCR_DBA ((uint16_t)0x001F) |
| #define | TIM_DCR_DBA_0 ((uint16_t)0x0001) |
| #define | TIM_DCR_DBA_1 ((uint16_t)0x0002) |
| #define | TIM_DCR_DBA_2 ((uint16_t)0x0004) |
| #define | TIM_DCR_DBA_3 ((uint16_t)0x0008) |
| #define | TIM_DCR_DBA_4 ((uint16_t)0x0010) |
| #define | TIM_DCR_DBL ((uint16_t)0x1F00) |
| #define | TIM_DCR_DBL_0 ((uint16_t)0x0100) |
| #define | TIM_DCR_DBL_1 ((uint16_t)0x0200) |
| #define | TIM_DCR_DBL_2 ((uint16_t)0x0400) |
| #define | TIM_DCR_DBL_3 ((uint16_t)0x0800) |
| #define | TIM_DCR_DBL_4 ((uint16_t)0x1000) |
| #define | TIM_DMAR_DMAB ((uint16_t)0xFFFF) |
| #define | TIM_OR_TI4_RMP ((uint16_t)0x00C0) |
| #define | TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) |
| #define | TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) |
| #define | TIM_OR_ITR1_RMP ((uint16_t)0x0C00) |
| #define | TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) |
| #define | TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) |
| #define | USART_SR_PE ((uint16_t)0x0001) |
| #define | USART_SR_FE ((uint16_t)0x0002) |
| #define | USART_SR_NE ((uint16_t)0x0004) |
| #define | USART_SR_ORE ((uint16_t)0x0008) |
| #define | USART_SR_IDLE ((uint16_t)0x0010) |
| #define | USART_SR_RXNE ((uint16_t)0x0020) |
| #define | USART_SR_TC ((uint16_t)0x0040) |
| #define | USART_SR_TXE ((uint16_t)0x0080) |
| #define | USART_SR_LBD ((uint16_t)0x0100) |
| #define | USART_SR_CTS ((uint16_t)0x0200) |
| #define | USART_DR_DR ((uint16_t)0x01FF) |
| #define | USART_BRR_DIV_Fraction ((uint16_t)0x000F) |
| #define | USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) |
| #define | USART_CR1_SBK ((uint16_t)0x0001) |
| #define | USART_CR1_RWU ((uint16_t)0x0002) |
| #define | USART_CR1_RE ((uint16_t)0x0004) |
| #define | USART_CR1_TE ((uint16_t)0x0008) |
| #define | USART_CR1_IDLEIE ((uint16_t)0x0010) |
| #define | USART_CR1_RXNEIE ((uint16_t)0x0020) |
| #define | USART_CR1_TCIE ((uint16_t)0x0040) |
| #define | USART_CR1_TXEIE ((uint16_t)0x0080) |
| #define | USART_CR1_PEIE ((uint16_t)0x0100) |
| #define | USART_CR1_PS ((uint16_t)0x0200) |
| #define | USART_CR1_PCE ((uint16_t)0x0400) |
| #define | USART_CR1_WAKE ((uint16_t)0x0800) |
| #define | USART_CR1_M ((uint16_t)0x1000) |
| #define | USART_CR1_UE ((uint16_t)0x2000) |
| #define | USART_CR1_OVER8 ((uint16_t)0x8000) |
| #define | USART_CR2_ADD ((uint16_t)0x000F) |
| #define | USART_CR2_LBDL ((uint16_t)0x0020) |
| #define | USART_CR2_LBDIE ((uint16_t)0x0040) |
| #define | USART_CR2_LBCL ((uint16_t)0x0100) |
| #define | USART_CR2_CPHA ((uint16_t)0x0200) |
| #define | USART_CR2_CPOL ((uint16_t)0x0400) |
| #define | USART_CR2_CLKEN ((uint16_t)0x0800) |
| #define | USART_CR2_STOP ((uint16_t)0x3000) |
| #define | USART_CR2_STOP_0 ((uint16_t)0x1000) |
| #define | USART_CR2_STOP_1 ((uint16_t)0x2000) |
| #define | USART_CR2_LINEN ((uint16_t)0x4000) |
| #define | USART_CR3_EIE ((uint16_t)0x0001) |
| #define | USART_CR3_IREN ((uint16_t)0x0002) |
| #define | USART_CR3_IRLP ((uint16_t)0x0004) |
| #define | USART_CR3_HDSEL ((uint16_t)0x0008) |
| #define | USART_CR3_NACK ((uint16_t)0x0010) |
| #define | USART_CR3_SCEN ((uint16_t)0x0020) |
| #define | USART_CR3_DMAR ((uint16_t)0x0040) |
| #define | USART_CR3_DMAT ((uint16_t)0x0080) |
| #define | USART_CR3_RTSE ((uint16_t)0x0100) |
| #define | USART_CR3_CTSE ((uint16_t)0x0200) |
| #define | USART_CR3_CTSIE ((uint16_t)0x0400) |
| #define | USART_CR3_ONEBIT ((uint16_t)0x0800) |
| #define | USART_GTPR_PSC ((uint16_t)0x00FF) |
| #define | USART_GTPR_PSC_0 ((uint16_t)0x0001) |
| #define | USART_GTPR_PSC_1 ((uint16_t)0x0002) |
| #define | USART_GTPR_PSC_2 ((uint16_t)0x0004) |
| #define | USART_GTPR_PSC_3 ((uint16_t)0x0008) |
| #define | USART_GTPR_PSC_4 ((uint16_t)0x0010) |
| #define | USART_GTPR_PSC_5 ((uint16_t)0x0020) |
| #define | USART_GTPR_PSC_6 ((uint16_t)0x0040) |
| #define | USART_GTPR_PSC_7 ((uint16_t)0x0080) |
| #define | USART_GTPR_GT ((uint16_t)0xFF00) |
| #define | WWDG_CR_T ((uint8_t)0x7F) |
| #define | WWDG_CR_T_0 ((uint8_t)0x01) |
| #define | WWDG_CR_T_1 ((uint8_t)0x02) |
| #define | WWDG_CR_T_2 ((uint8_t)0x04) |
| #define | WWDG_CR_T_3 ((uint8_t)0x08) |
| #define | WWDG_CR_T_4 ((uint8_t)0x10) |
| #define | WWDG_CR_T_5 ((uint8_t)0x20) |
| #define | WWDG_CR_T_6 ((uint8_t)0x40) |
| #define | WWDG_CR_T0 WWDG_CR_T_0 |
| #define | WWDG_CR_T1 WWDG_CR_T_1 |
| #define | WWDG_CR_T2 WWDG_CR_T_2 |
| #define | WWDG_CR_T3 WWDG_CR_T_3 |
| #define | WWDG_CR_T4 WWDG_CR_T_4 |
| #define | WWDG_CR_T5 WWDG_CR_T_5 |
| #define | WWDG_CR_T6 WWDG_CR_T_6 |
| #define | WWDG_CR_WDGA ((uint8_t)0x80) |
| #define | WWDG_CFR_W ((uint16_t)0x007F) |
| #define | WWDG_CFR_W_0 ((uint16_t)0x0001) |
| #define | WWDG_CFR_W_1 ((uint16_t)0x0002) |
| #define | WWDG_CFR_W_2 ((uint16_t)0x0004) |
| #define | WWDG_CFR_W_3 ((uint16_t)0x0008) |
| #define | WWDG_CFR_W_4 ((uint16_t)0x0010) |
| #define | WWDG_CFR_W_5 ((uint16_t)0x0020) |
| #define | WWDG_CFR_W_6 ((uint16_t)0x0040) |
| #define | WWDG_CFR_W0 WWDG_CFR_W_0 |
| #define | WWDG_CFR_W1 WWDG_CFR_W_1 |
| #define | WWDG_CFR_W2 WWDG_CFR_W_2 |
| #define | WWDG_CFR_W3 WWDG_CFR_W_3 |
| #define | WWDG_CFR_W4 WWDG_CFR_W_4 |
| #define | WWDG_CFR_W5 WWDG_CFR_W_5 |
| #define | WWDG_CFR_W6 WWDG_CFR_W_6 |
| #define | WWDG_CFR_WDGTB ((uint16_t)0x0180) |
| #define | WWDG_CFR_WDGTB_0 ((uint16_t)0x0080) |
| #define | WWDG_CFR_WDGTB_1 ((uint16_t)0x0100) |
| #define | WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 |
| #define | WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 |
| #define | WWDG_CFR_EWI ((uint16_t)0x0200) |
| #define | WWDG_SR_EWIF ((uint8_t)0x01) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040 |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080 |
| #define | DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) |
| #define | DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) |
| #define | DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) |
| #define | DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) |
| #define | DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) |
| #define | DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040) |
| #define | DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080) |
| #define | DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) |
| #define | DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) |
| #define | DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000) |
| #define | DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP |
| #define | DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) |
| #define | DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB1_FZ_DBG_TIM1_STOP |
| #define | DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB1_FZ_DBG_TIM8_STOP |
| #define | DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000) |
| #define | DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB1_FZ_DBG_TIM9_STOP |
| #define | DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000) |
| #define | DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB1_FZ_DBG_TIM10_STOP |
| #define | DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000) |
| #define | DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB1_FZ_DBG_TIM11_STOP |
| #define | ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ |
| #define | ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ |
| #define | ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ |
| #define | ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ |
| #define | ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ |
| #define | ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ |
| #define | ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ |
| #define | ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ |
| #define | ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ |
| #define | ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ |
| #define | ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ |
| #define | ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ |
| #define | ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ |
| #define | ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ |
| #define | ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ |
| #define | ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ |
| #define | ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ |
| #define | ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ |
| #define | ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ |
| #define | ETH_MACCR_BL |
| #define | ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ |
| #define | ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ |
| #define | ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ |
| #define | ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ |
| #define | ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ |
| #define | ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ |
| #define | ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ |
| #define | ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ |
| #define | ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ |
| #define | ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ |
| #define | ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ |
| #define | ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ |
| #define | ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ |
| #define | ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ |
| #define | ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ |
| #define | ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ |
| #define | ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ |
| #define | ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ |
| #define | ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ |
| #define | ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ |
| #define | ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ |
| #define | ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ |
| #define | ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ |
| #define | ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ |
| #define | ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ |
| #define | ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ |
| #define | ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ |
| #define | ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ |
| #define | ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
| #define | ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
| #define | ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ |
| #define | ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ |
| #define | ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ |
| #define | ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ |
| #define | ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ |
| #define | ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ |
| #define | ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ |
| #define | ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ |
| #define | ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ |
| #define | ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ |
| #define | ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ |
| #define | ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ |
| #define | ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ |
| #define | ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ |
| #define | ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ |
| #define | ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ |
| #define | ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ |
| #define | ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ |
| #define | ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ |
| #define | ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ |
| #define | ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ |
| #define | ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ |
| #define | ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ |
| #define | ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ |
| #define | ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ |
| #define | ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ |
| #define | ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ |
| #define | ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ |
| #define | ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ |
| #define | ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ |
| #define | ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ |
| #define | ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ |
| #define | ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ |
| #define | ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ |
| #define | ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
| #define | ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ |
| #define | ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
| #define | ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ |
| #define | ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
| #define | ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
| #define | ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
| #define | ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ |
| #define | ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
| #define | ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
| #define | ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ |
| #define | ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ |
| #define | ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */ |
| #define | ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */ |
| #define | ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ |
| #define | ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ |
| #define | ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ |
| #define | ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ |
| #define | ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ |
| #define | ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ |
| #define | ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
| #define | ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
| #define | ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
| #define | ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ |
| #define | ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ |
| #define | ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ |
| #define | ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ |
| #define | ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */ |
| #define | ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */ |
| #define | ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */ |
| #define | ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ |
| #define | ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ |
| #define | ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ |
| #define | ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ |
| #define | ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */ |
| #define | ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */ |
| #define | ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ |
| #define | ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ |
| #define | ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ |
| #define | ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ |
| #define | ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ |
| #define | ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ |
| #define | ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ |
| #define | ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ |
| #define | ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ |
| #define | ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ |
| #define | ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ |
| #define | ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ |
| #define | ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ |
| #define | ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ |
| #define | ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ |
| #define | ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ |
| #define | ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */ |
| #define | ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */ |
| #define | ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ |
| #define | ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ |
| #define | ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ |
| #define | ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ |
| #define | ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
| #define | ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
| #define | ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| #define | ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| #define | ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| #define | ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| #define | ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| #define | ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| #define | ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| #define | ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| #define | ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
| #define | ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
| #define | ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ |
| #define | ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ |
| #define | ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
| #define | ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
| #define | ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| #define | ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| #define | ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| #define | ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| #define | ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| #define | ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| #define | ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| #define | ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| #define | ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
| #define | ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
| #define | ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */ |
| #define | ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ |
| #define | ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ |
| #define | ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ |
| #define | ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ |
| #define | ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ |
| #define | ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ |
| #define | ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ |
| #define | ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ |
| #define | ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ |
| #define | ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ |
| #define | ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ |
| #define | ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ |
| #define | ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ |
| #define | ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ |
| #define | ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ |
| #define | ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ |
| #define | ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ |
| #define | ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ |
| #define | ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ |
| #define | ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ |
| #define | ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ |
| #define | ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ |
| #define | ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ |
| #define | ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ |
| #define | ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ |
| #define | ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ |
| #define | ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ |
| #define | ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ |
| #define | ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ |
| #define | ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ |
| #define | ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ |
| #define | ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ |
| #define | ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ |
| #define | ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ |
| #define | ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ |
| #define | ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ |
| #define | ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ |
| #define | ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ |
| #define | ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ |
| #define | ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ |
| #define | ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ |
| #define | ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ |
| #define | ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ |
| #define | ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ |
| #define | ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ |
| #define | ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ |
| #define | ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ |
| #define | ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ |
| #define | ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ |
| #define | ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
| #define | ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
| #define | ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
| #define | ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
| #define | ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
| #define | ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
| #define | ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
| #define | ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
| #define | ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ |
| #define | ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ |
| #define | ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ |
| #define | ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ |
| #define | ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
| #define | ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
| #define | ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
| #define | ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
| #define | ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ |
| #define | ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ |
| #define | ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ |
| #define | ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ |
| #define | ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ |
| #define | ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ |
| #define | ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ |
| #define | ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ |
| #define | ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ |
| #define | ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ |
| #define | ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ |
| #define | ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ |
| #define | ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ |
| #define | ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ |
| #define | ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ |
| #define | ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ |
| #define | ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ |
| #define | ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ |
| #define | ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ |
| #define | ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ |
| #define | ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ |
| #define | ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ |
| #define | ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ |
| #define | ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ |
| #define | ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ |
| #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) |
ADCPRE[1:0] bits (ADC prescaler)
Definition at line 2811 of file stm32f4xx.h.
| #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 2812 of file stm32f4xx.h.
| #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 2813 of file stm32f4xx.h.
| #define ADC_CCR_DDS ((uint32_t)0x00002000) |
DMA disable selection (Multi-ADC mode)
Definition at line 2807 of file stm32f4xx.h.
Referenced by ADC_MultiModeDMARequestAfterLastTransferCmd().
| #define ADC_CCR_DELAY ((uint32_t)0x00000F00) |
DELAY[3:0] bits (Delay between 2 sampling phases)
Definition at line 2802 of file stm32f4xx.h.
| #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 2803 of file stm32f4xx.h.
| #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 2804 of file stm32f4xx.h.
| #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 2805 of file stm32f4xx.h.
| #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 2806 of file stm32f4xx.h.
| #define ADC_CCR_DMA ((uint32_t)0x0000C000) |
DMA[1:0] bits (Direct Memory Access mode for multimode)
Definition at line 2808 of file stm32f4xx.h.
| #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) |
Bit 0
Definition at line 2809 of file stm32f4xx.h.
| #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) |
Bit 1
Definition at line 2810 of file stm32f4xx.h.
| #define ADC_CCR_MULTI ((uint32_t)0x0000001F) |
MULTI[4:0] bits (Multi-ADC mode selection)
Definition at line 2796 of file stm32f4xx.h.
| #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 2797 of file stm32f4xx.h.
| #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 2798 of file stm32f4xx.h.
| #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 2799 of file stm32f4xx.h.
| #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 2800 of file stm32f4xx.h.
| #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 2801 of file stm32f4xx.h.
| #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) |
Temperature Sensor and VREFINT Enable
Definition at line 2815 of file stm32f4xx.h.
Referenced by ADC_TempSensorVrefintCmd().
| #define ADC_CCR_VBATE ((uint32_t)0x00400000) |
| #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) |
1st data of a pair of regular conversions
Definition at line 2818 of file stm32f4xx.h.
| #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) |
2nd data of a pair of regular conversions
Definition at line 2819 of file stm32f4xx.h.
| #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
AWDCH[4:0] bits (Analog watchdog channel select bits)
Definition at line 2469 of file stm32f4xx.h.
| #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 2470 of file stm32f4xx.h.
| #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 2471 of file stm32f4xx.h.
| #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 2472 of file stm32f4xx.h.
| #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 2473 of file stm32f4xx.h.
| #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 2474 of file stm32f4xx.h.
| #define ADC_CR1_AWDEN ((uint32_t)0x00800000) |
Analog watchdog enable on regular channels
Definition at line 2488 of file stm32f4xx.h.
| #define ADC_CR1_AWDIE ((uint32_t)0x00000040) |
AAnalog Watchdog interrupt enable
Definition at line 2476 of file stm32f4xx.h.
| #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
Enable the watchdog on a single channel in scan mode
Definition at line 2479 of file stm32f4xx.h.
| #define ADC_CR1_DISCEN ((uint32_t)0x00000800) |
Discontinuous mode on regular channels
Definition at line 2481 of file stm32f4xx.h.
Referenced by ADC_DiscModeCmd().
| #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
DISCNUM[2:0] bits (Discontinuous mode channel count)
Definition at line 2483 of file stm32f4xx.h.
| #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
Bit 0
Definition at line 2484 of file stm32f4xx.h.
| #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
Bit 1
Definition at line 2485 of file stm32f4xx.h.
| #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
Bit 2
Definition at line 2486 of file stm32f4xx.h.
| #define ADC_CR1_EOCIE ((uint32_t)0x00000020) |
Interrupt enable for EOC
Definition at line 2475 of file stm32f4xx.h.
| #define ADC_CR1_JAUTO ((uint32_t)0x00000400) |
Automatic injected group conversion
Definition at line 2480 of file stm32f4xx.h.
Referenced by ADC_AutoInjectedConvCmd().
| #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
Analog watchdog enable on injected channels
Definition at line 2487 of file stm32f4xx.h.
| #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
Discontinuous mode on injected channels
Definition at line 2482 of file stm32f4xx.h.
Referenced by ADC_InjectedDiscModeCmd().
| #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
Interrupt enable for injected channels
Definition at line 2477 of file stm32f4xx.h.
| #define ADC_CR1_OVRIE ((uint32_t)0x04000000) |
overrun interrupt enable
Definition at line 2492 of file stm32f4xx.h.
| #define ADC_CR1_RES ((uint32_t)0x03000000) |
RES[2:0] bits (Resolution)
Definition at line 2489 of file stm32f4xx.h.
| #define ADC_CR1_RES_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 2490 of file stm32f4xx.h.
| #define ADC_CR1_RES_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 2491 of file stm32f4xx.h.
| #define ADC_CR1_SCAN ((uint32_t)0x00000100) |
Scan mode
Definition at line 2478 of file stm32f4xx.h.
| #define ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define ADC_CR2_ALIGN ((uint32_t)0x00000800) |
Data Alignment
Definition at line 2500 of file stm32f4xx.h.
| #define ADC_CR2_CONT ((uint32_t)0x00000002) |
Continuous Conversion
Definition at line 2496 of file stm32f4xx.h.
Referenced by ADC_ContinuousModeCmd().
| #define ADC_CR2_DDS ((uint32_t)0x00000200) |
DMA disable selection (Single ADC)
Definition at line 2498 of file stm32f4xx.h.
Referenced by ADC_DMARequestAfterLastTransferCmd().
| #define ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define ADC_CR2_EOCS ((uint32_t)0x00000400) |
End of conversion selection
Definition at line 2499 of file stm32f4xx.h.
Referenced by ADC_EOCOnEachRegularChannelCmd().
| #define ADC_CR2_EXTEN ((uint32_t)0x30000000) |
EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp)
Definition at line 2515 of file stm32f4xx.h.
| #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) |
Bit 0
Definition at line 2516 of file stm32f4xx.h.
| #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) |
Bit 1
Definition at line 2517 of file stm32f4xx.h.
| #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) |
EXTSEL[3:0] bits (External Event Select for regular group)
Definition at line 2510 of file stm32f4xx.h.
| #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 2511 of file stm32f4xx.h.
| #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 2512 of file stm32f4xx.h.
| #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 2513 of file stm32f4xx.h.
| #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 2514 of file stm32f4xx.h.
| #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) |
JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp)
Definition at line 2506 of file stm32f4xx.h.
| #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 2507 of file stm32f4xx.h.
| #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 2508 of file stm32f4xx.h.
| #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) |
JEXTSEL[3:0] bits (External event select for injected group)
Definition at line 2501 of file stm32f4xx.h.
| #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 2502 of file stm32f4xx.h.
| #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 2503 of file stm32f4xx.h.
| #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) |
Bit 2
Definition at line 2504 of file stm32f4xx.h.
| #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) |
Bit 3
Definition at line 2505 of file stm32f4xx.h.
| #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) |
Start Conversion of injected channels
Definition at line 2509 of file stm32f4xx.h.
Referenced by ADC_GetSoftwareStartInjectedConvCmdStatus(), and ADC_SoftwareStartInjectedConv().
| #define ADC_CR2_SWSTART ((uint32_t)0x40000000) |
Start Conversion of regular channels
Definition at line 2518 of file stm32f4xx.h.
Referenced by ADC_GetSoftwareStartConvStatus(), and ADC_SoftwareStartConv().
| #define ADC_CSR_AWD1 ((uint32_t)0x00000001) |
ADC1 Analog watchdog flag
Definition at line 2771 of file stm32f4xx.h.
| #define ADC_CSR_AWD2 ((uint32_t)0x00000100) |
ADC2 Analog watchdog flag
Definition at line 2777 of file stm32f4xx.h.
| #define ADC_CSR_AWD3 ((uint32_t)0x00010000) |
ADC3 Analog watchdog flag
Definition at line 2783 of file stm32f4xx.h.
| #define ADC_CSR_DOVR1 ADC_CSR_OVR1 |
Definition at line 2791 of file stm32f4xx.h.
| #define ADC_CSR_DOVR2 ADC_CSR_OVR2 |
Definition at line 2792 of file stm32f4xx.h.
| #define ADC_CSR_DOVR3 ADC_CSR_OVR3 |
Definition at line 2793 of file stm32f4xx.h.
| #define ADC_CSR_EOC1 ((uint32_t)0x00000002) |
ADC1 End of conversion
Definition at line 2772 of file stm32f4xx.h.
| #define ADC_CSR_EOC2 ((uint32_t)0x00000200) |
ADC2 End of conversion
Definition at line 2778 of file stm32f4xx.h.
| #define ADC_CSR_EOC3 ((uint32_t)0x00020000) |
ADC3 End of conversion
Definition at line 2784 of file stm32f4xx.h.
| #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) |
ADC1 Injected channel end of conversion
Definition at line 2773 of file stm32f4xx.h.
| #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) |
ADC2 Injected channel end of conversion
Definition at line 2779 of file stm32f4xx.h.
| #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) |
ADC3 Injected channel end of conversion
Definition at line 2785 of file stm32f4xx.h.
| #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) |
ADC1 Injected channel Start flag
Definition at line 2774 of file stm32f4xx.h.
| #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) |
ADC2 Injected channel Start flag
Definition at line 2780 of file stm32f4xx.h.
| #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) |
ADC3 Injected channel Start flag
Definition at line 2786 of file stm32f4xx.h.
| #define ADC_CSR_OVR1 ((uint32_t)0x00000020) |
ADC1 DMA overrun flag
Definition at line 2776 of file stm32f4xx.h.
| #define ADC_CSR_OVR2 ((uint32_t)0x00002000) |
ADC2 DMA overrun flag
Definition at line 2782 of file stm32f4xx.h.
| #define ADC_CSR_OVR3 ((uint32_t)0x00200000) |
ADC3 DMA overrun flag
Definition at line 2788 of file stm32f4xx.h.
| #define ADC_CSR_STRT1 ((uint32_t)0x00000010) |
ADC1 Regular channel Start flag
Definition at line 2775 of file stm32f4xx.h.
| #define ADC_CSR_STRT2 ((uint32_t)0x00001000) |
ADC2 Regular channel Start flag
Definition at line 2781 of file stm32f4xx.h.
| #define ADC_CSR_STRT3 ((uint32_t)0x00100000) |
ADC3 Regular channel Start flag
Definition at line 2787 of file stm32f4xx.h.
| #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
ADC2 data
Definition at line 2768 of file stm32f4xx.h.
| #define ADC_DR_DATA ((uint32_t)0x0000FFFF) |
Regular data
Definition at line 2767 of file stm32f4xx.h.
| #define ADC_HTR_HT ((uint16_t)0x0FFF) |
Analog watchdog high threshold
Definition at line 2613 of file stm32f4xx.h.
| #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) |
Injected data
Definition at line 2755 of file stm32f4xx.h.
| #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) |
Injected data
Definition at line 2758 of file stm32f4xx.h.
| #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) |
Injected data
Definition at line 2761 of file stm32f4xx.h.
| #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) |
Injected data
Definition at line 2764 of file stm32f4xx.h.
| #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) |
Data offset for injected channel 1
Definition at line 2601 of file stm32f4xx.h.
| #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) |
Data offset for injected channel 2
Definition at line 2604 of file stm32f4xx.h.
| #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) |
Data offset for injected channel 3
Definition at line 2607 of file stm32f4xx.h.
| #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) |
Data offset for injected channel 4
Definition at line 2610 of file stm32f4xx.h.
| #define ADC_JSQR_JL ((uint32_t)0x00300000) |
JL[1:0] bits (Injected Sequence length)
Definition at line 2750 of file stm32f4xx.h.
| #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 2751 of file stm32f4xx.h.
| #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 2752 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
JSQ1[4:0] bits (1st conversion in injected sequence)
Definition at line 2726 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 2727 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 2728 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 2729 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 2730 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 2731 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
JSQ2[4:0] bits (2nd conversion in injected sequence)
Definition at line 2732 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
Bit 0
Definition at line 2733 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
Bit 1
Definition at line 2734 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
Bit 2
Definition at line 2735 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
Bit 3
Definition at line 2736 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
Bit 4
Definition at line 2737 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
JSQ3[4:0] bits (3rd conversion in injected sequence)
Definition at line 2738 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
Bit 0
Definition at line 2739 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
Bit 1
Definition at line 2740 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
Bit 2
Definition at line 2741 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
Bit 3
Definition at line 2742 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
Bit 4
Definition at line 2743 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
JSQ4[4:0] bits (4th conversion in injected sequence)
Definition at line 2744 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
Bit 0
Definition at line 2745 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
Bit 1
Definition at line 2746 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
Bit 2
Definition at line 2747 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
Bit 3
Definition at line 2748 of file stm32f4xx.h.
| #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
Bit 4
Definition at line 2749 of file stm32f4xx.h.
| #define ADC_LTR_LT ((uint16_t)0x0FFF) |
Analog watchdog low threshold
Definition at line 2616 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
SMP10[2:0] bits (Channel 10 Sample time selection)
Definition at line 2521 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 2522 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 2523 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 2524 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
SMP11[2:0] bits (Channel 11 Sample time selection)
Definition at line 2525 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
Bit 0
Definition at line 2526 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
Bit 1
Definition at line 2527 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
Bit 2
Definition at line 2528 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
SMP12[2:0] bits (Channel 12 Sample time selection)
Definition at line 2529 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
Bit 0
Definition at line 2530 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
Bit 1
Definition at line 2531 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
Bit 2
Definition at line 2532 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
SMP13[2:0] bits (Channel 13 Sample time selection)
Definition at line 2533 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
Bit 0
Definition at line 2534 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
Bit 1
Definition at line 2535 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
Bit 2
Definition at line 2536 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
SMP14[2:0] bits (Channel 14 Sample time selection)
Definition at line 2537 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
Bit 0
Definition at line 2538 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
Bit 1
Definition at line 2539 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
Bit 2
Definition at line 2540 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
SMP15[2:0] bits (Channel 15 Sample time selection)
Definition at line 2541 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
Bit 0
Definition at line 2542 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
Bit 1
Definition at line 2543 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
Bit 2
Definition at line 2544 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
SMP16[2:0] bits (Channel 16 Sample time selection)
Definition at line 2545 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
Bit 0
Definition at line 2546 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
Bit 1
Definition at line 2547 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
Bit 2
Definition at line 2548 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
SMP17[2:0] bits (Channel 17 Sample time selection)
Definition at line 2549 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
Bit 0
Definition at line 2550 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
Bit 1
Definition at line 2551 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
Bit 2
Definition at line 2552 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) |
SMP18[2:0] bits (Channel 18 Sample time selection)
Definition at line 2553 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 2554 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 2555 of file stm32f4xx.h.
| #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 2556 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
SMP0[2:0] bits (Channel 0 Sample time selection)
Definition at line 2559 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 2560 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 2561 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 2562 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
SMP1[2:0] bits (Channel 1 Sample time selection)
Definition at line 2563 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
Bit 0
Definition at line 2564 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
Bit 1
Definition at line 2565 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
Bit 2
Definition at line 2566 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
SMP2[2:0] bits (Channel 2 Sample time selection)
Definition at line 2567 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
Bit 0
Definition at line 2568 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
Bit 1
Definition at line 2569 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
Bit 2
Definition at line 2570 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
SMP3[2:0] bits (Channel 3 Sample time selection)
Definition at line 2571 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
Bit 0
Definition at line 2572 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
Bit 1
Definition at line 2573 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
Bit 2
Definition at line 2574 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
SMP4[2:0] bits (Channel 4 Sample time selection)
Definition at line 2575 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
Bit 0
Definition at line 2576 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
Bit 1
Definition at line 2577 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
Bit 2
Definition at line 2578 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
SMP5[2:0] bits (Channel 5 Sample time selection)
Definition at line 2579 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
Bit 0
Definition at line 2580 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
Bit 1
Definition at line 2581 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
Bit 2
Definition at line 2582 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
SMP6[2:0] bits (Channel 6 Sample time selection)
Definition at line 2583 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
Bit 0
Definition at line 2584 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
Bit 1
Definition at line 2585 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
Bit 2
Definition at line 2586 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
SMP7[2:0] bits (Channel 7 Sample time selection)
Definition at line 2587 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
Bit 0
Definition at line 2588 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
Bit 1
Definition at line 2589 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
Bit 2
Definition at line 2590 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
SMP8[2:0] bits (Channel 8 Sample time selection)
Definition at line 2591 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 2592 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 2593 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 2594 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
SMP9[2:0] bits (Channel 9 Sample time selection)
Definition at line 2595 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
Bit 0
Definition at line 2596 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
Bit 1
Definition at line 2597 of file stm32f4xx.h.
| #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
Bit 2
Definition at line 2598 of file stm32f4xx.h.
| #define ADC_SQR1_L ((uint32_t)0x00F00000) |
L[3:0] bits (Regular channel sequence length)
Definition at line 2643 of file stm32f4xx.h.
| #define ADC_SQR1_L_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 2644 of file stm32f4xx.h.
| #define ADC_SQR1_L_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 2645 of file stm32f4xx.h.
| #define ADC_SQR1_L_2 ((uint32_t)0x00400000) |
Bit 2
Definition at line 2646 of file stm32f4xx.h.
| #define ADC_SQR1_L_3 ((uint32_t)0x00800000) |
Bit 3
Definition at line 2647 of file stm32f4xx.h.
| #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
SQ13[4:0] bits (13th conversion in regular sequence)
Definition at line 2619 of file stm32f4xx.h.
| #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 2620 of file stm32f4xx.h.
| #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 2621 of file stm32f4xx.h.
| #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 2622 of file stm32f4xx.h.
| #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 2623 of file stm32f4xx.h.
| #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 2624 of file stm32f4xx.h.
| #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
SQ14[4:0] bits (14th conversion in regular sequence)
Definition at line 2625 of file stm32f4xx.h.
| #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
Bit 0
Definition at line 2626 of file stm32f4xx.h.
| #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
Bit 1
Definition at line 2627 of file stm32f4xx.h.
| #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
Bit 2
Definition at line 2628 of file stm32f4xx.h.
| #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
Bit 3
Definition at line 2629 of file stm32f4xx.h.
| #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
Bit 4
Definition at line 2630 of file stm32f4xx.h.
| #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
SQ15[4:0] bits (15th conversion in regular sequence)
Definition at line 2631 of file stm32f4xx.h.
| #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
Bit 0
Definition at line 2632 of file stm32f4xx.h.
| #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
Bit 1
Definition at line 2633 of file stm32f4xx.h.
| #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
Bit 2
Definition at line 2634 of file stm32f4xx.h.
| #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
Bit 3
Definition at line 2635 of file stm32f4xx.h.
| #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
Bit 4
Definition at line 2636 of file stm32f4xx.h.
| #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
SQ16[4:0] bits (16th conversion in regular sequence)
Definition at line 2637 of file stm32f4xx.h.
| #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
Bit 0
Definition at line 2638 of file stm32f4xx.h.
| #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
Bit 1
Definition at line 2639 of file stm32f4xx.h.
| #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
Bit 2
Definition at line 2640 of file stm32f4xx.h.
| #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
Bit 3
Definition at line 2641 of file stm32f4xx.h.
| #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
Bit 4
Definition at line 2642 of file stm32f4xx.h.
| #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
SQ10[4:0] bits (10th conversion in regular sequence)
Definition at line 2668 of file stm32f4xx.h.
| #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
Bit 0
Definition at line 2669 of file stm32f4xx.h.
| #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
Bit 1
Definition at line 2670 of file stm32f4xx.h.
| #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
Bit 2
Definition at line 2671 of file stm32f4xx.h.
| #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
Bit 3
Definition at line 2672 of file stm32f4xx.h.
| #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
Bit 4
Definition at line 2673 of file stm32f4xx.h.
| #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
SQ11[4:0] bits (11th conversion in regular sequence)
Definition at line 2674 of file stm32f4xx.h.
| #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 2675 of file stm32f4xx.h.
| #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 2676 of file stm32f4xx.h.
| #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
Bit 2
Definition at line 2677 of file stm32f4xx.h.
| #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
Bit 3
Definition at line 2678 of file stm32f4xx.h.
| #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
Bit 4
Definition at line 2679 of file stm32f4xx.h.
| #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
SQ12[4:0] bits (12th conversion in regular sequence)
Definition at line 2680 of file stm32f4xx.h.
| #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
Bit 0
Definition at line 2681 of file stm32f4xx.h.
| #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
Bit 1
Definition at line 2682 of file stm32f4xx.h.
| #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
Bit 2
Definition at line 2683 of file stm32f4xx.h.
| #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
Bit 3
Definition at line 2684 of file stm32f4xx.h.
| #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
Bit 4
Definition at line 2685 of file stm32f4xx.h.
| #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
SQ7[4:0] bits (7th conversion in regular sequence)
Definition at line 2650 of file stm32f4xx.h.
| #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 2651 of file stm32f4xx.h.
| #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 2652 of file stm32f4xx.h.
| #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 2653 of file stm32f4xx.h.
| #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 2654 of file stm32f4xx.h.
| #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 2655 of file stm32f4xx.h.
| #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
SQ8[4:0] bits (8th conversion in regular sequence)
Definition at line 2656 of file stm32f4xx.h.
| #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
Bit 0
Definition at line 2657 of file stm32f4xx.h.
| #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
Bit 1
Definition at line 2658 of file stm32f4xx.h.
| #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
Bit 2
Definition at line 2659 of file stm32f4xx.h.
| #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
Bit 3
Definition at line 2660 of file stm32f4xx.h.
| #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
Bit 4
Definition at line 2661 of file stm32f4xx.h.
| #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
SQ9[4:0] bits (9th conversion in regular sequence)
Definition at line 2662 of file stm32f4xx.h.
| #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
Bit 0
Definition at line 2663 of file stm32f4xx.h.
| #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
Bit 1
Definition at line 2664 of file stm32f4xx.h.
| #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
Bit 2
Definition at line 2665 of file stm32f4xx.h.
| #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
Bit 3
Definition at line 2666 of file stm32f4xx.h.
| #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
Bit 4
Definition at line 2667 of file stm32f4xx.h.
| #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
SQ1[4:0] bits (1st conversion in regular sequence)
Definition at line 2688 of file stm32f4xx.h.
| #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 2689 of file stm32f4xx.h.
| #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 2690 of file stm32f4xx.h.
| #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 2691 of file stm32f4xx.h.
| #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 2692 of file stm32f4xx.h.
| #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 2693 of file stm32f4xx.h.
| #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
SQ2[4:0] bits (2nd conversion in regular sequence)
Definition at line 2694 of file stm32f4xx.h.
| #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
Bit 0
Definition at line 2695 of file stm32f4xx.h.
| #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
Bit 1
Definition at line 2696 of file stm32f4xx.h.
| #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
Bit 2
Definition at line 2697 of file stm32f4xx.h.
| #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
Bit 3
Definition at line 2698 of file stm32f4xx.h.
| #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
Bit 4
Definition at line 2699 of file stm32f4xx.h.
| #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
SQ3[4:0] bits (3rd conversion in regular sequence)
Definition at line 2700 of file stm32f4xx.h.
| #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
Bit 0
Definition at line 2701 of file stm32f4xx.h.
| #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
Bit 1
Definition at line 2702 of file stm32f4xx.h.
| #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
Bit 2
Definition at line 2703 of file stm32f4xx.h.
| #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
Bit 3
Definition at line 2704 of file stm32f4xx.h.
| #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
Bit 4
Definition at line 2705 of file stm32f4xx.h.
| #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
SQ4[4:0] bits (4th conversion in regular sequence)
Definition at line 2706 of file stm32f4xx.h.
| #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
Bit 0
Definition at line 2707 of file stm32f4xx.h.
| #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
Bit 1
Definition at line 2708 of file stm32f4xx.h.
| #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
Bit 2
Definition at line 2709 of file stm32f4xx.h.
| #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
Bit 3
Definition at line 2710 of file stm32f4xx.h.
| #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
Bit 4
Definition at line 2711 of file stm32f4xx.h.
| #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
SQ5[4:0] bits (5th conversion in regular sequence)
Definition at line 2712 of file stm32f4xx.h.
| #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
Bit 0
Definition at line 2713 of file stm32f4xx.h.
| #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
Bit 1
Definition at line 2714 of file stm32f4xx.h.
| #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
Bit 2
Definition at line 2715 of file stm32f4xx.h.
| #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
Bit 3
Definition at line 2716 of file stm32f4xx.h.
| #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
Bit 4
Definition at line 2717 of file stm32f4xx.h.
| #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
SQ6[4:0] bits (6th conversion in regular sequence)
Definition at line 2718 of file stm32f4xx.h.
| #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
Bit 0
Definition at line 2719 of file stm32f4xx.h.
| #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
Bit 1
Definition at line 2720 of file stm32f4xx.h.
| #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
Bit 2
Definition at line 2721 of file stm32f4xx.h.
| #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
Bit 3
Definition at line 2722 of file stm32f4xx.h.
| #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
Bit 4
Definition at line 2723 of file stm32f4xx.h.
| #define ADC_SR_AWD ((uint8_t)0x01) |
Analog watchdog flag
Definition at line 2461 of file stm32f4xx.h.
| #define ADC_SR_EOC ((uint8_t)0x02) |
End of conversion
Definition at line 2462 of file stm32f4xx.h.
| #define ADC_SR_JEOC ((uint8_t)0x04) |
Injected channel end of conversion
Definition at line 2463 of file stm32f4xx.h.
| #define ADC_SR_JSTRT ((uint8_t)0x08) |
Injected channel Start flag
Definition at line 2464 of file stm32f4xx.h.
| #define ADC_SR_OVR ((uint8_t)0x20) |
Overrun flag
Definition at line 2466 of file stm32f4xx.h.
| #define ADC_SR_STRT ((uint8_t)0x10) |
Regular channel Start flag
Definition at line 2465 of file stm32f4xx.h.
| #define CAN_BTR_BRP ((uint32_t)0x000003FF) |
Baud Rate Prescaler
Definition at line 2919 of file stm32f4xx.h.
| #define CAN_BTR_LBKM ((uint32_t)0x40000000) |
Loop Back Mode (Debug)
Definition at line 2923 of file stm32f4xx.h.
| #define CAN_BTR_SILM ((uint32_t)0x80000000) |
Silent Mode Mailbox registers
Definition at line 2924 of file stm32f4xx.h.
| #define CAN_BTR_SJW ((uint32_t)0x03000000) |
Resynchronization Jump Width
Definition at line 2922 of file stm32f4xx.h.
| #define CAN_BTR_TS1 ((uint32_t)0x000F0000) |
Time Segment 1
Definition at line 2920 of file stm32f4xx.h.
| #define CAN_BTR_TS2 ((uint32_t)0x00700000) |
Time Segment 2
Definition at line 2921 of file stm32f4xx.h.
| #define CAN_ESR_BOFF ((uint32_t)0x00000004) |
| #define CAN_ESR_EPVF ((uint32_t)0x00000002) |
| #define CAN_ESR_EWGF ((uint32_t)0x00000001) |
| #define CAN_ESR_LEC ((uint32_t)0x00000070) |
LEC[2:0] bits (Last Error Code)
Definition at line 2910 of file stm32f4xx.h.
Referenced by CAN_GetITStatus(), and CAN_GetLastErrorCode().
| #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 2911 of file stm32f4xx.h.
| #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 2912 of file stm32f4xx.h.
| #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
Bit 2
Definition at line 2913 of file stm32f4xx.h.
| #define CAN_ESR_REC ((uint32_t)0xFF000000) |
Receive Error Counter
Definition at line 2916 of file stm32f4xx.h.
Referenced by CAN_GetReceiveErrorCounter().
| #define CAN_ESR_TEC ((uint32_t)0x00FF0000) |
Least significant byte of the 9-bit Transmit Error Counter
Definition at line 2915 of file stm32f4xx.h.
Referenced by CAN_GetLSBTransmitErrorCounter().
| #define CAN_F0R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3118 of file stm32f4xx.h.
| #define CAN_F0R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3119 of file stm32f4xx.h.
| #define CAN_F0R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3128 of file stm32f4xx.h.
| #define CAN_F0R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3129 of file stm32f4xx.h.
| #define CAN_F0R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3130 of file stm32f4xx.h.
| #define CAN_F0R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3131 of file stm32f4xx.h.
| #define CAN_F0R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3132 of file stm32f4xx.h.
| #define CAN_F0R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3133 of file stm32f4xx.h.
| #define CAN_F0R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3134 of file stm32f4xx.h.
| #define CAN_F0R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3135 of file stm32f4xx.h.
| #define CAN_F0R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3136 of file stm32f4xx.h.
| #define CAN_F0R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3137 of file stm32f4xx.h.
| #define CAN_F0R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3120 of file stm32f4xx.h.
| #define CAN_F0R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3138 of file stm32f4xx.h.
| #define CAN_F0R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3139 of file stm32f4xx.h.
| #define CAN_F0R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3140 of file stm32f4xx.h.
| #define CAN_F0R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3141 of file stm32f4xx.h.
| #define CAN_F0R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3142 of file stm32f4xx.h.
| #define CAN_F0R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3143 of file stm32f4xx.h.
| #define CAN_F0R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3144 of file stm32f4xx.h.
| #define CAN_F0R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3145 of file stm32f4xx.h.
| #define CAN_F0R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3146 of file stm32f4xx.h.
| #define CAN_F0R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3147 of file stm32f4xx.h.
| #define CAN_F0R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3121 of file stm32f4xx.h.
| #define CAN_F0R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3148 of file stm32f4xx.h.
| #define CAN_F0R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3149 of file stm32f4xx.h.
| #define CAN_F0R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3122 of file stm32f4xx.h.
| #define CAN_F0R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3123 of file stm32f4xx.h.
| #define CAN_F0R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3124 of file stm32f4xx.h.
| #define CAN_F0R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3125 of file stm32f4xx.h.
| #define CAN_F0R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3126 of file stm32f4xx.h.
| #define CAN_F0R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3127 of file stm32f4xx.h.
| #define CAN_F0R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3594 of file stm32f4xx.h.
| #define CAN_F0R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3595 of file stm32f4xx.h.
| #define CAN_F0R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3604 of file stm32f4xx.h.
| #define CAN_F0R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3605 of file stm32f4xx.h.
| #define CAN_F0R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3606 of file stm32f4xx.h.
| #define CAN_F0R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3607 of file stm32f4xx.h.
| #define CAN_F0R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3608 of file stm32f4xx.h.
| #define CAN_F0R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3609 of file stm32f4xx.h.
| #define CAN_F0R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3610 of file stm32f4xx.h.
| #define CAN_F0R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3611 of file stm32f4xx.h.
| #define CAN_F0R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3612 of file stm32f4xx.h.
| #define CAN_F0R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3613 of file stm32f4xx.h.
| #define CAN_F0R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3596 of file stm32f4xx.h.
| #define CAN_F0R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3614 of file stm32f4xx.h.
| #define CAN_F0R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3615 of file stm32f4xx.h.
| #define CAN_F0R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3616 of file stm32f4xx.h.
| #define CAN_F0R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3617 of file stm32f4xx.h.
| #define CAN_F0R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3618 of file stm32f4xx.h.
| #define CAN_F0R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3619 of file stm32f4xx.h.
| #define CAN_F0R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3620 of file stm32f4xx.h.
| #define CAN_F0R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3621 of file stm32f4xx.h.
| #define CAN_F0R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3622 of file stm32f4xx.h.
| #define CAN_F0R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3623 of file stm32f4xx.h.
| #define CAN_F0R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3597 of file stm32f4xx.h.
| #define CAN_F0R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3624 of file stm32f4xx.h.
| #define CAN_F0R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3625 of file stm32f4xx.h.
| #define CAN_F0R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3598 of file stm32f4xx.h.
| #define CAN_F0R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3599 of file stm32f4xx.h.
| #define CAN_F0R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3600 of file stm32f4xx.h.
| #define CAN_F0R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3601 of file stm32f4xx.h.
| #define CAN_F0R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3602 of file stm32f4xx.h.
| #define CAN_F0R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3603 of file stm32f4xx.h.
| #define CAN_F10R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3458 of file stm32f4xx.h.
| #define CAN_F10R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3459 of file stm32f4xx.h.
| #define CAN_F10R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3468 of file stm32f4xx.h.
| #define CAN_F10R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3469 of file stm32f4xx.h.
| #define CAN_F10R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3470 of file stm32f4xx.h.
| #define CAN_F10R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3471 of file stm32f4xx.h.
| #define CAN_F10R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3472 of file stm32f4xx.h.
| #define CAN_F10R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3473 of file stm32f4xx.h.
| #define CAN_F10R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3474 of file stm32f4xx.h.
| #define CAN_F10R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3475 of file stm32f4xx.h.
| #define CAN_F10R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3476 of file stm32f4xx.h.
| #define CAN_F10R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3477 of file stm32f4xx.h.
| #define CAN_F10R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3460 of file stm32f4xx.h.
| #define CAN_F10R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3478 of file stm32f4xx.h.
| #define CAN_F10R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3479 of file stm32f4xx.h.
| #define CAN_F10R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3480 of file stm32f4xx.h.
| #define CAN_F10R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3481 of file stm32f4xx.h.
| #define CAN_F10R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3482 of file stm32f4xx.h.
| #define CAN_F10R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3483 of file stm32f4xx.h.
| #define CAN_F10R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3484 of file stm32f4xx.h.
| #define CAN_F10R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3485 of file stm32f4xx.h.
| #define CAN_F10R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3486 of file stm32f4xx.h.
| #define CAN_F10R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3487 of file stm32f4xx.h.
| #define CAN_F10R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3461 of file stm32f4xx.h.
| #define CAN_F10R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3488 of file stm32f4xx.h.
| #define CAN_F10R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3489 of file stm32f4xx.h.
| #define CAN_F10R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3462 of file stm32f4xx.h.
| #define CAN_F10R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3463 of file stm32f4xx.h.
| #define CAN_F10R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3464 of file stm32f4xx.h.
| #define CAN_F10R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3465 of file stm32f4xx.h.
| #define CAN_F10R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3466 of file stm32f4xx.h.
| #define CAN_F10R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3467 of file stm32f4xx.h.
| #define CAN_F10R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3934 of file stm32f4xx.h.
| #define CAN_F10R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3935 of file stm32f4xx.h.
| #define CAN_F10R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3944 of file stm32f4xx.h.
| #define CAN_F10R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3945 of file stm32f4xx.h.
| #define CAN_F10R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3946 of file stm32f4xx.h.
| #define CAN_F10R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3947 of file stm32f4xx.h.
| #define CAN_F10R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3948 of file stm32f4xx.h.
| #define CAN_F10R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3949 of file stm32f4xx.h.
| #define CAN_F10R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3950 of file stm32f4xx.h.
| #define CAN_F10R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3951 of file stm32f4xx.h.
| #define CAN_F10R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3952 of file stm32f4xx.h.
| #define CAN_F10R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3953 of file stm32f4xx.h.
| #define CAN_F10R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3936 of file stm32f4xx.h.
| #define CAN_F10R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3954 of file stm32f4xx.h.
| #define CAN_F10R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3955 of file stm32f4xx.h.
| #define CAN_F10R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3956 of file stm32f4xx.h.
| #define CAN_F10R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3957 of file stm32f4xx.h.
| #define CAN_F10R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3958 of file stm32f4xx.h.
| #define CAN_F10R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3959 of file stm32f4xx.h.
| #define CAN_F10R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3960 of file stm32f4xx.h.
| #define CAN_F10R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3961 of file stm32f4xx.h.
| #define CAN_F10R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3962 of file stm32f4xx.h.
| #define CAN_F10R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3963 of file stm32f4xx.h.
| #define CAN_F10R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3937 of file stm32f4xx.h.
| #define CAN_F10R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3964 of file stm32f4xx.h.
| #define CAN_F10R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3965 of file stm32f4xx.h.
| #define CAN_F10R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3938 of file stm32f4xx.h.
| #define CAN_F10R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3939 of file stm32f4xx.h.
| #define CAN_F10R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3940 of file stm32f4xx.h.
| #define CAN_F10R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3941 of file stm32f4xx.h.
| #define CAN_F10R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3942 of file stm32f4xx.h.
| #define CAN_F10R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3943 of file stm32f4xx.h.
| #define CAN_F11R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3492 of file stm32f4xx.h.
| #define CAN_F11R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3493 of file stm32f4xx.h.
| #define CAN_F11R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3502 of file stm32f4xx.h.
| #define CAN_F11R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3503 of file stm32f4xx.h.
| #define CAN_F11R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3504 of file stm32f4xx.h.
| #define CAN_F11R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3505 of file stm32f4xx.h.
| #define CAN_F11R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3506 of file stm32f4xx.h.
| #define CAN_F11R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3507 of file stm32f4xx.h.
| #define CAN_F11R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3508 of file stm32f4xx.h.
| #define CAN_F11R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3509 of file stm32f4xx.h.
| #define CAN_F11R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3510 of file stm32f4xx.h.
| #define CAN_F11R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3511 of file stm32f4xx.h.
| #define CAN_F11R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3494 of file stm32f4xx.h.
| #define CAN_F11R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3512 of file stm32f4xx.h.
| #define CAN_F11R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3513 of file stm32f4xx.h.
| #define CAN_F11R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3514 of file stm32f4xx.h.
| #define CAN_F11R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3515 of file stm32f4xx.h.
| #define CAN_F11R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3516 of file stm32f4xx.h.
| #define CAN_F11R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3517 of file stm32f4xx.h.
| #define CAN_F11R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3518 of file stm32f4xx.h.
| #define CAN_F11R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3519 of file stm32f4xx.h.
| #define CAN_F11R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3520 of file stm32f4xx.h.
| #define CAN_F11R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3521 of file stm32f4xx.h.
| #define CAN_F11R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3495 of file stm32f4xx.h.
| #define CAN_F11R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3522 of file stm32f4xx.h.
| #define CAN_F11R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3523 of file stm32f4xx.h.
| #define CAN_F11R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3496 of file stm32f4xx.h.
| #define CAN_F11R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3497 of file stm32f4xx.h.
| #define CAN_F11R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3498 of file stm32f4xx.h.
| #define CAN_F11R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3499 of file stm32f4xx.h.
| #define CAN_F11R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3500 of file stm32f4xx.h.
| #define CAN_F11R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3501 of file stm32f4xx.h.
| #define CAN_F11R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3968 of file stm32f4xx.h.
| #define CAN_F11R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3969 of file stm32f4xx.h.
| #define CAN_F11R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3978 of file stm32f4xx.h.
| #define CAN_F11R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3979 of file stm32f4xx.h.
| #define CAN_F11R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3980 of file stm32f4xx.h.
| #define CAN_F11R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3981 of file stm32f4xx.h.
| #define CAN_F11R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3982 of file stm32f4xx.h.
| #define CAN_F11R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3983 of file stm32f4xx.h.
| #define CAN_F11R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3984 of file stm32f4xx.h.
| #define CAN_F11R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3985 of file stm32f4xx.h.
| #define CAN_F11R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3986 of file stm32f4xx.h.
| #define CAN_F11R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3987 of file stm32f4xx.h.
| #define CAN_F11R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3970 of file stm32f4xx.h.
| #define CAN_F11R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3988 of file stm32f4xx.h.
| #define CAN_F11R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3989 of file stm32f4xx.h.
| #define CAN_F11R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3990 of file stm32f4xx.h.
| #define CAN_F11R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3991 of file stm32f4xx.h.
| #define CAN_F11R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3992 of file stm32f4xx.h.
| #define CAN_F11R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3993 of file stm32f4xx.h.
| #define CAN_F11R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3994 of file stm32f4xx.h.
| #define CAN_F11R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3995 of file stm32f4xx.h.
| #define CAN_F11R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3996 of file stm32f4xx.h.
| #define CAN_F11R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3997 of file stm32f4xx.h.
| #define CAN_F11R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3971 of file stm32f4xx.h.
| #define CAN_F11R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3998 of file stm32f4xx.h.
| #define CAN_F11R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3999 of file stm32f4xx.h.
| #define CAN_F11R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3972 of file stm32f4xx.h.
| #define CAN_F11R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3973 of file stm32f4xx.h.
| #define CAN_F11R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3974 of file stm32f4xx.h.
| #define CAN_F11R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3975 of file stm32f4xx.h.
| #define CAN_F11R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3976 of file stm32f4xx.h.
| #define CAN_F11R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3977 of file stm32f4xx.h.
| #define CAN_F12R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3526 of file stm32f4xx.h.
| #define CAN_F12R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3527 of file stm32f4xx.h.
| #define CAN_F12R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3536 of file stm32f4xx.h.
| #define CAN_F12R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3537 of file stm32f4xx.h.
| #define CAN_F12R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3538 of file stm32f4xx.h.
| #define CAN_F12R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3539 of file stm32f4xx.h.
| #define CAN_F12R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3540 of file stm32f4xx.h.
| #define CAN_F12R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3541 of file stm32f4xx.h.
| #define CAN_F12R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3542 of file stm32f4xx.h.
| #define CAN_F12R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3543 of file stm32f4xx.h.
| #define CAN_F12R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3544 of file stm32f4xx.h.
| #define CAN_F12R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3545 of file stm32f4xx.h.
| #define CAN_F12R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3528 of file stm32f4xx.h.
| #define CAN_F12R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3546 of file stm32f4xx.h.
| #define CAN_F12R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3547 of file stm32f4xx.h.
| #define CAN_F12R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3548 of file stm32f4xx.h.
| #define CAN_F12R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3549 of file stm32f4xx.h.
| #define CAN_F12R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3550 of file stm32f4xx.h.
| #define CAN_F12R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3551 of file stm32f4xx.h.
| #define CAN_F12R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3552 of file stm32f4xx.h.
| #define CAN_F12R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3553 of file stm32f4xx.h.
| #define CAN_F12R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3554 of file stm32f4xx.h.
| #define CAN_F12R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3555 of file stm32f4xx.h.
| #define CAN_F12R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3529 of file stm32f4xx.h.
| #define CAN_F12R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3556 of file stm32f4xx.h.
| #define CAN_F12R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3557 of file stm32f4xx.h.
| #define CAN_F12R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3530 of file stm32f4xx.h.
| #define CAN_F12R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3531 of file stm32f4xx.h.
| #define CAN_F12R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3532 of file stm32f4xx.h.
| #define CAN_F12R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3533 of file stm32f4xx.h.
| #define CAN_F12R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3534 of file stm32f4xx.h.
| #define CAN_F12R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3535 of file stm32f4xx.h.
| #define CAN_F12R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 4002 of file stm32f4xx.h.
| #define CAN_F12R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 4003 of file stm32f4xx.h.
| #define CAN_F12R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 4012 of file stm32f4xx.h.
| #define CAN_F12R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 4013 of file stm32f4xx.h.
| #define CAN_F12R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 4014 of file stm32f4xx.h.
| #define CAN_F12R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 4015 of file stm32f4xx.h.
| #define CAN_F12R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 4016 of file stm32f4xx.h.
| #define CAN_F12R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 4017 of file stm32f4xx.h.
| #define CAN_F12R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 4018 of file stm32f4xx.h.
| #define CAN_F12R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 4019 of file stm32f4xx.h.
| #define CAN_F12R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 4020 of file stm32f4xx.h.
| #define CAN_F12R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 4021 of file stm32f4xx.h.
| #define CAN_F12R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 4004 of file stm32f4xx.h.
| #define CAN_F12R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 4022 of file stm32f4xx.h.
| #define CAN_F12R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 4023 of file stm32f4xx.h.
| #define CAN_F12R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 4024 of file stm32f4xx.h.
| #define CAN_F12R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 4025 of file stm32f4xx.h.
| #define CAN_F12R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 4026 of file stm32f4xx.h.
| #define CAN_F12R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 4027 of file stm32f4xx.h.
| #define CAN_F12R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 4028 of file stm32f4xx.h.
| #define CAN_F12R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 4029 of file stm32f4xx.h.
| #define CAN_F12R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 4030 of file stm32f4xx.h.
| #define CAN_F12R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 4031 of file stm32f4xx.h.
| #define CAN_F12R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 4005 of file stm32f4xx.h.
| #define CAN_F12R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 4032 of file stm32f4xx.h.
| #define CAN_F12R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 4033 of file stm32f4xx.h.
| #define CAN_F12R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 4006 of file stm32f4xx.h.
| #define CAN_F12R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 4007 of file stm32f4xx.h.
| #define CAN_F12R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 4008 of file stm32f4xx.h.
| #define CAN_F12R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 4009 of file stm32f4xx.h.
| #define CAN_F12R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 4010 of file stm32f4xx.h.
| #define CAN_F12R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 4011 of file stm32f4xx.h.
| #define CAN_F13R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3560 of file stm32f4xx.h.
| #define CAN_F13R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3561 of file stm32f4xx.h.
| #define CAN_F13R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3570 of file stm32f4xx.h.
| #define CAN_F13R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3571 of file stm32f4xx.h.
| #define CAN_F13R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3572 of file stm32f4xx.h.
| #define CAN_F13R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3573 of file stm32f4xx.h.
| #define CAN_F13R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3574 of file stm32f4xx.h.
| #define CAN_F13R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3575 of file stm32f4xx.h.
| #define CAN_F13R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3576 of file stm32f4xx.h.
| #define CAN_F13R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3577 of file stm32f4xx.h.
| #define CAN_F13R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3578 of file stm32f4xx.h.
| #define CAN_F13R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3579 of file stm32f4xx.h.
| #define CAN_F13R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3562 of file stm32f4xx.h.
| #define CAN_F13R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3580 of file stm32f4xx.h.
| #define CAN_F13R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3581 of file stm32f4xx.h.
| #define CAN_F13R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3582 of file stm32f4xx.h.
| #define CAN_F13R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3583 of file stm32f4xx.h.
| #define CAN_F13R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3584 of file stm32f4xx.h.
| #define CAN_F13R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3585 of file stm32f4xx.h.
| #define CAN_F13R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3586 of file stm32f4xx.h.
| #define CAN_F13R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3587 of file stm32f4xx.h.
| #define CAN_F13R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3588 of file stm32f4xx.h.
| #define CAN_F13R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3589 of file stm32f4xx.h.
| #define CAN_F13R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3563 of file stm32f4xx.h.
| #define CAN_F13R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3590 of file stm32f4xx.h.
| #define CAN_F13R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3591 of file stm32f4xx.h.
| #define CAN_F13R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3564 of file stm32f4xx.h.
| #define CAN_F13R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3565 of file stm32f4xx.h.
| #define CAN_F13R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3566 of file stm32f4xx.h.
| #define CAN_F13R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3567 of file stm32f4xx.h.
| #define CAN_F13R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3568 of file stm32f4xx.h.
| #define CAN_F13R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3569 of file stm32f4xx.h.
| #define CAN_F13R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 4036 of file stm32f4xx.h.
| #define CAN_F13R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 4037 of file stm32f4xx.h.
| #define CAN_F13R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 4046 of file stm32f4xx.h.
| #define CAN_F13R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 4047 of file stm32f4xx.h.
| #define CAN_F13R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 4048 of file stm32f4xx.h.
| #define CAN_F13R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 4049 of file stm32f4xx.h.
| #define CAN_F13R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 4050 of file stm32f4xx.h.
| #define CAN_F13R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 4051 of file stm32f4xx.h.
| #define CAN_F13R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 4052 of file stm32f4xx.h.
| #define CAN_F13R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 4053 of file stm32f4xx.h.
| #define CAN_F13R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 4054 of file stm32f4xx.h.
| #define CAN_F13R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 4055 of file stm32f4xx.h.
| #define CAN_F13R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 4038 of file stm32f4xx.h.
| #define CAN_F13R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 4056 of file stm32f4xx.h.
| #define CAN_F13R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 4057 of file stm32f4xx.h.
| #define CAN_F13R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 4058 of file stm32f4xx.h.
| #define CAN_F13R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 4059 of file stm32f4xx.h.
| #define CAN_F13R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 4060 of file stm32f4xx.h.
| #define CAN_F13R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 4061 of file stm32f4xx.h.
| #define CAN_F13R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 4062 of file stm32f4xx.h.
| #define CAN_F13R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 4063 of file stm32f4xx.h.
| #define CAN_F13R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 4064 of file stm32f4xx.h.
| #define CAN_F13R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 4065 of file stm32f4xx.h.
| #define CAN_F13R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 4039 of file stm32f4xx.h.
| #define CAN_F13R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 4066 of file stm32f4xx.h.
| #define CAN_F13R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 4067 of file stm32f4xx.h.
| #define CAN_F13R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 4040 of file stm32f4xx.h.
| #define CAN_F13R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 4041 of file stm32f4xx.h.
| #define CAN_F13R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 4042 of file stm32f4xx.h.
| #define CAN_F13R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 4043 of file stm32f4xx.h.
| #define CAN_F13R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 4044 of file stm32f4xx.h.
| #define CAN_F13R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 4045 of file stm32f4xx.h.
| #define CAN_F1R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3152 of file stm32f4xx.h.
| #define CAN_F1R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3153 of file stm32f4xx.h.
| #define CAN_F1R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3162 of file stm32f4xx.h.
| #define CAN_F1R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3163 of file stm32f4xx.h.
| #define CAN_F1R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3164 of file stm32f4xx.h.
| #define CAN_F1R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3165 of file stm32f4xx.h.
| #define CAN_F1R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3166 of file stm32f4xx.h.
| #define CAN_F1R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3167 of file stm32f4xx.h.
| #define CAN_F1R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3168 of file stm32f4xx.h.
| #define CAN_F1R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3169 of file stm32f4xx.h.
| #define CAN_F1R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3170 of file stm32f4xx.h.
| #define CAN_F1R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3171 of file stm32f4xx.h.
| #define CAN_F1R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3154 of file stm32f4xx.h.
| #define CAN_F1R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3172 of file stm32f4xx.h.
| #define CAN_F1R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3173 of file stm32f4xx.h.
| #define CAN_F1R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3174 of file stm32f4xx.h.
| #define CAN_F1R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3175 of file stm32f4xx.h.
| #define CAN_F1R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3176 of file stm32f4xx.h.
| #define CAN_F1R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3177 of file stm32f4xx.h.
| #define CAN_F1R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3178 of file stm32f4xx.h.
| #define CAN_F1R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3179 of file stm32f4xx.h.
| #define CAN_F1R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3180 of file stm32f4xx.h.
| #define CAN_F1R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3181 of file stm32f4xx.h.
| #define CAN_F1R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3155 of file stm32f4xx.h.
| #define CAN_F1R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3182 of file stm32f4xx.h.
| #define CAN_F1R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3183 of file stm32f4xx.h.
| #define CAN_F1R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3156 of file stm32f4xx.h.
| #define CAN_F1R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3157 of file stm32f4xx.h.
| #define CAN_F1R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3158 of file stm32f4xx.h.
| #define CAN_F1R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3159 of file stm32f4xx.h.
| #define CAN_F1R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3160 of file stm32f4xx.h.
| #define CAN_F1R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3161 of file stm32f4xx.h.
| #define CAN_F1R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3628 of file stm32f4xx.h.
| #define CAN_F1R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3629 of file stm32f4xx.h.
| #define CAN_F1R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3638 of file stm32f4xx.h.
| #define CAN_F1R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3639 of file stm32f4xx.h.
| #define CAN_F1R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3640 of file stm32f4xx.h.
| #define CAN_F1R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3641 of file stm32f4xx.h.
| #define CAN_F1R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3642 of file stm32f4xx.h.
| #define CAN_F1R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3643 of file stm32f4xx.h.
| #define CAN_F1R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3644 of file stm32f4xx.h.
| #define CAN_F1R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3645 of file stm32f4xx.h.
| #define CAN_F1R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3646 of file stm32f4xx.h.
| #define CAN_F1R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3647 of file stm32f4xx.h.
| #define CAN_F1R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3630 of file stm32f4xx.h.
| #define CAN_F1R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3648 of file stm32f4xx.h.
| #define CAN_F1R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3649 of file stm32f4xx.h.
| #define CAN_F1R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3650 of file stm32f4xx.h.
| #define CAN_F1R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3651 of file stm32f4xx.h.
| #define CAN_F1R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3652 of file stm32f4xx.h.
| #define CAN_F1R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3653 of file stm32f4xx.h.
| #define CAN_F1R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3654 of file stm32f4xx.h.
| #define CAN_F1R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3655 of file stm32f4xx.h.
| #define CAN_F1R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3656 of file stm32f4xx.h.
| #define CAN_F1R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3657 of file stm32f4xx.h.
| #define CAN_F1R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3631 of file stm32f4xx.h.
| #define CAN_F1R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3658 of file stm32f4xx.h.
| #define CAN_F1R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3659 of file stm32f4xx.h.
| #define CAN_F1R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3632 of file stm32f4xx.h.
| #define CAN_F1R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3633 of file stm32f4xx.h.
| #define CAN_F1R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3634 of file stm32f4xx.h.
| #define CAN_F1R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3635 of file stm32f4xx.h.
| #define CAN_F1R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3636 of file stm32f4xx.h.
| #define CAN_F1R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3637 of file stm32f4xx.h.
| #define CAN_F2R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3186 of file stm32f4xx.h.
| #define CAN_F2R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3187 of file stm32f4xx.h.
| #define CAN_F2R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3196 of file stm32f4xx.h.
| #define CAN_F2R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3197 of file stm32f4xx.h.
| #define CAN_F2R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3198 of file stm32f4xx.h.
| #define CAN_F2R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3199 of file stm32f4xx.h.
| #define CAN_F2R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3200 of file stm32f4xx.h.
| #define CAN_F2R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3201 of file stm32f4xx.h.
| #define CAN_F2R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3202 of file stm32f4xx.h.
| #define CAN_F2R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3203 of file stm32f4xx.h.
| #define CAN_F2R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3204 of file stm32f4xx.h.
| #define CAN_F2R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3205 of file stm32f4xx.h.
| #define CAN_F2R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3188 of file stm32f4xx.h.
| #define CAN_F2R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3206 of file stm32f4xx.h.
| #define CAN_F2R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3207 of file stm32f4xx.h.
| #define CAN_F2R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3208 of file stm32f4xx.h.
| #define CAN_F2R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3209 of file stm32f4xx.h.
| #define CAN_F2R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3210 of file stm32f4xx.h.
| #define CAN_F2R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3211 of file stm32f4xx.h.
| #define CAN_F2R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3212 of file stm32f4xx.h.
| #define CAN_F2R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3213 of file stm32f4xx.h.
| #define CAN_F2R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3214 of file stm32f4xx.h.
| #define CAN_F2R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3215 of file stm32f4xx.h.
| #define CAN_F2R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3189 of file stm32f4xx.h.
| #define CAN_F2R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3216 of file stm32f4xx.h.
| #define CAN_F2R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3217 of file stm32f4xx.h.
| #define CAN_F2R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3190 of file stm32f4xx.h.
| #define CAN_F2R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3191 of file stm32f4xx.h.
| #define CAN_F2R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3192 of file stm32f4xx.h.
| #define CAN_F2R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3193 of file stm32f4xx.h.
| #define CAN_F2R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3194 of file stm32f4xx.h.
| #define CAN_F2R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3195 of file stm32f4xx.h.
| #define CAN_F2R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3662 of file stm32f4xx.h.
| #define CAN_F2R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3663 of file stm32f4xx.h.
| #define CAN_F2R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3672 of file stm32f4xx.h.
| #define CAN_F2R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3673 of file stm32f4xx.h.
| #define CAN_F2R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3674 of file stm32f4xx.h.
| #define CAN_F2R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3675 of file stm32f4xx.h.
| #define CAN_F2R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3676 of file stm32f4xx.h.
| #define CAN_F2R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3677 of file stm32f4xx.h.
| #define CAN_F2R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3678 of file stm32f4xx.h.
| #define CAN_F2R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3679 of file stm32f4xx.h.
| #define CAN_F2R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3680 of file stm32f4xx.h.
| #define CAN_F2R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3681 of file stm32f4xx.h.
| #define CAN_F2R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3664 of file stm32f4xx.h.
| #define CAN_F2R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3682 of file stm32f4xx.h.
| #define CAN_F2R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3683 of file stm32f4xx.h.
| #define CAN_F2R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3684 of file stm32f4xx.h.
| #define CAN_F2R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3685 of file stm32f4xx.h.
| #define CAN_F2R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3686 of file stm32f4xx.h.
| #define CAN_F2R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3687 of file stm32f4xx.h.
| #define CAN_F2R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3688 of file stm32f4xx.h.
| #define CAN_F2R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3689 of file stm32f4xx.h.
| #define CAN_F2R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3690 of file stm32f4xx.h.
| #define CAN_F2R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3691 of file stm32f4xx.h.
| #define CAN_F2R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3665 of file stm32f4xx.h.
| #define CAN_F2R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3692 of file stm32f4xx.h.
| #define CAN_F2R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3693 of file stm32f4xx.h.
| #define CAN_F2R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3666 of file stm32f4xx.h.
| #define CAN_F2R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3667 of file stm32f4xx.h.
| #define CAN_F2R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3668 of file stm32f4xx.h.
| #define CAN_F2R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3669 of file stm32f4xx.h.
| #define CAN_F2R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3670 of file stm32f4xx.h.
| #define CAN_F2R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3671 of file stm32f4xx.h.
| #define CAN_F3R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3220 of file stm32f4xx.h.
| #define CAN_F3R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3221 of file stm32f4xx.h.
| #define CAN_F3R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3230 of file stm32f4xx.h.
| #define CAN_F3R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3231 of file stm32f4xx.h.
| #define CAN_F3R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3232 of file stm32f4xx.h.
| #define CAN_F3R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3233 of file stm32f4xx.h.
| #define CAN_F3R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3234 of file stm32f4xx.h.
| #define CAN_F3R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3235 of file stm32f4xx.h.
| #define CAN_F3R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3236 of file stm32f4xx.h.
| #define CAN_F3R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3237 of file stm32f4xx.h.
| #define CAN_F3R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3238 of file stm32f4xx.h.
| #define CAN_F3R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3239 of file stm32f4xx.h.
| #define CAN_F3R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3222 of file stm32f4xx.h.
| #define CAN_F3R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3240 of file stm32f4xx.h.
| #define CAN_F3R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3241 of file stm32f4xx.h.
| #define CAN_F3R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3242 of file stm32f4xx.h.
| #define CAN_F3R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3243 of file stm32f4xx.h.
| #define CAN_F3R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3244 of file stm32f4xx.h.
| #define CAN_F3R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3245 of file stm32f4xx.h.
| #define CAN_F3R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3246 of file stm32f4xx.h.
| #define CAN_F3R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3247 of file stm32f4xx.h.
| #define CAN_F3R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3248 of file stm32f4xx.h.
| #define CAN_F3R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3249 of file stm32f4xx.h.
| #define CAN_F3R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3223 of file stm32f4xx.h.
| #define CAN_F3R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3250 of file stm32f4xx.h.
| #define CAN_F3R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3251 of file stm32f4xx.h.
| #define CAN_F3R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3224 of file stm32f4xx.h.
| #define CAN_F3R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3225 of file stm32f4xx.h.
| #define CAN_F3R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3226 of file stm32f4xx.h.
| #define CAN_F3R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3227 of file stm32f4xx.h.
| #define CAN_F3R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3228 of file stm32f4xx.h.
| #define CAN_F3R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3229 of file stm32f4xx.h.
| #define CAN_F3R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3696 of file stm32f4xx.h.
| #define CAN_F3R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3697 of file stm32f4xx.h.
| #define CAN_F3R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3706 of file stm32f4xx.h.
| #define CAN_F3R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3707 of file stm32f4xx.h.
| #define CAN_F3R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3708 of file stm32f4xx.h.
| #define CAN_F3R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3709 of file stm32f4xx.h.
| #define CAN_F3R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3710 of file stm32f4xx.h.
| #define CAN_F3R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3711 of file stm32f4xx.h.
| #define CAN_F3R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3712 of file stm32f4xx.h.
| #define CAN_F3R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3713 of file stm32f4xx.h.
| #define CAN_F3R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3714 of file stm32f4xx.h.
| #define CAN_F3R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3715 of file stm32f4xx.h.
| #define CAN_F3R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3698 of file stm32f4xx.h.
| #define CAN_F3R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3716 of file stm32f4xx.h.
| #define CAN_F3R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3717 of file stm32f4xx.h.
| #define CAN_F3R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3718 of file stm32f4xx.h.
| #define CAN_F3R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3719 of file stm32f4xx.h.
| #define CAN_F3R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3720 of file stm32f4xx.h.
| #define CAN_F3R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3721 of file stm32f4xx.h.
| #define CAN_F3R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3722 of file stm32f4xx.h.
| #define CAN_F3R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3723 of file stm32f4xx.h.
| #define CAN_F3R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3724 of file stm32f4xx.h.
| #define CAN_F3R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3725 of file stm32f4xx.h.
| #define CAN_F3R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3699 of file stm32f4xx.h.
| #define CAN_F3R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3726 of file stm32f4xx.h.
| #define CAN_F3R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3727 of file stm32f4xx.h.
| #define CAN_F3R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3700 of file stm32f4xx.h.
| #define CAN_F3R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3701 of file stm32f4xx.h.
| #define CAN_F3R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3702 of file stm32f4xx.h.
| #define CAN_F3R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3703 of file stm32f4xx.h.
| #define CAN_F3R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3704 of file stm32f4xx.h.
| #define CAN_F3R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3705 of file stm32f4xx.h.
| #define CAN_F4R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3254 of file stm32f4xx.h.
| #define CAN_F4R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3255 of file stm32f4xx.h.
| #define CAN_F4R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3264 of file stm32f4xx.h.
| #define CAN_F4R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3265 of file stm32f4xx.h.
| #define CAN_F4R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3266 of file stm32f4xx.h.
| #define CAN_F4R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3267 of file stm32f4xx.h.
| #define CAN_F4R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3268 of file stm32f4xx.h.
| #define CAN_F4R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3269 of file stm32f4xx.h.
| #define CAN_F4R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3270 of file stm32f4xx.h.
| #define CAN_F4R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3271 of file stm32f4xx.h.
| #define CAN_F4R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3272 of file stm32f4xx.h.
| #define CAN_F4R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3273 of file stm32f4xx.h.
| #define CAN_F4R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3256 of file stm32f4xx.h.
| #define CAN_F4R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3274 of file stm32f4xx.h.
| #define CAN_F4R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3275 of file stm32f4xx.h.
| #define CAN_F4R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3276 of file stm32f4xx.h.
| #define CAN_F4R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3277 of file stm32f4xx.h.
| #define CAN_F4R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3278 of file stm32f4xx.h.
| #define CAN_F4R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3279 of file stm32f4xx.h.
| #define CAN_F4R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3280 of file stm32f4xx.h.
| #define CAN_F4R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3281 of file stm32f4xx.h.
| #define CAN_F4R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3282 of file stm32f4xx.h.
| #define CAN_F4R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3283 of file stm32f4xx.h.
| #define CAN_F4R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3257 of file stm32f4xx.h.
| #define CAN_F4R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3284 of file stm32f4xx.h.
| #define CAN_F4R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3285 of file stm32f4xx.h.
| #define CAN_F4R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3258 of file stm32f4xx.h.
| #define CAN_F4R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3259 of file stm32f4xx.h.
| #define CAN_F4R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3260 of file stm32f4xx.h.
| #define CAN_F4R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3261 of file stm32f4xx.h.
| #define CAN_F4R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3262 of file stm32f4xx.h.
| #define CAN_F4R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3263 of file stm32f4xx.h.
| #define CAN_F4R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3730 of file stm32f4xx.h.
| #define CAN_F4R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3731 of file stm32f4xx.h.
| #define CAN_F4R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3740 of file stm32f4xx.h.
| #define CAN_F4R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3741 of file stm32f4xx.h.
| #define CAN_F4R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3742 of file stm32f4xx.h.
| #define CAN_F4R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3743 of file stm32f4xx.h.
| #define CAN_F4R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3744 of file stm32f4xx.h.
| #define CAN_F4R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3745 of file stm32f4xx.h.
| #define CAN_F4R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3746 of file stm32f4xx.h.
| #define CAN_F4R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3747 of file stm32f4xx.h.
| #define CAN_F4R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3748 of file stm32f4xx.h.
| #define CAN_F4R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3749 of file stm32f4xx.h.
| #define CAN_F4R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3732 of file stm32f4xx.h.
| #define CAN_F4R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3750 of file stm32f4xx.h.
| #define CAN_F4R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3751 of file stm32f4xx.h.
| #define CAN_F4R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3752 of file stm32f4xx.h.
| #define CAN_F4R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3753 of file stm32f4xx.h.
| #define CAN_F4R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3754 of file stm32f4xx.h.
| #define CAN_F4R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3755 of file stm32f4xx.h.
| #define CAN_F4R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3756 of file stm32f4xx.h.
| #define CAN_F4R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3757 of file stm32f4xx.h.
| #define CAN_F4R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3758 of file stm32f4xx.h.
| #define CAN_F4R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3759 of file stm32f4xx.h.
| #define CAN_F4R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3733 of file stm32f4xx.h.
| #define CAN_F4R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3760 of file stm32f4xx.h.
| #define CAN_F4R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3761 of file stm32f4xx.h.
| #define CAN_F4R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3734 of file stm32f4xx.h.
| #define CAN_F4R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3735 of file stm32f4xx.h.
| #define CAN_F4R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3736 of file stm32f4xx.h.
| #define CAN_F4R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3737 of file stm32f4xx.h.
| #define CAN_F4R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3738 of file stm32f4xx.h.
| #define CAN_F4R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3739 of file stm32f4xx.h.
| #define CAN_F5R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3288 of file stm32f4xx.h.
| #define CAN_F5R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3289 of file stm32f4xx.h.
| #define CAN_F5R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3298 of file stm32f4xx.h.
| #define CAN_F5R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3299 of file stm32f4xx.h.
| #define CAN_F5R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3300 of file stm32f4xx.h.
| #define CAN_F5R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3301 of file stm32f4xx.h.
| #define CAN_F5R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3302 of file stm32f4xx.h.
| #define CAN_F5R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3303 of file stm32f4xx.h.
| #define CAN_F5R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3304 of file stm32f4xx.h.
| #define CAN_F5R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3305 of file stm32f4xx.h.
| #define CAN_F5R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3306 of file stm32f4xx.h.
| #define CAN_F5R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3307 of file stm32f4xx.h.
| #define CAN_F5R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3290 of file stm32f4xx.h.
| #define CAN_F5R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3308 of file stm32f4xx.h.
| #define CAN_F5R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3309 of file stm32f4xx.h.
| #define CAN_F5R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3310 of file stm32f4xx.h.
| #define CAN_F5R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3311 of file stm32f4xx.h.
| #define CAN_F5R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3312 of file stm32f4xx.h.
| #define CAN_F5R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3313 of file stm32f4xx.h.
| #define CAN_F5R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3314 of file stm32f4xx.h.
| #define CAN_F5R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3315 of file stm32f4xx.h.
| #define CAN_F5R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3316 of file stm32f4xx.h.
| #define CAN_F5R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3317 of file stm32f4xx.h.
| #define CAN_F5R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3291 of file stm32f4xx.h.
| #define CAN_F5R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3318 of file stm32f4xx.h.
| #define CAN_F5R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3319 of file stm32f4xx.h.
| #define CAN_F5R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3292 of file stm32f4xx.h.
| #define CAN_F5R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3293 of file stm32f4xx.h.
| #define CAN_F5R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3294 of file stm32f4xx.h.
| #define CAN_F5R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3295 of file stm32f4xx.h.
| #define CAN_F5R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3296 of file stm32f4xx.h.
| #define CAN_F5R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3297 of file stm32f4xx.h.
| #define CAN_F5R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3764 of file stm32f4xx.h.
| #define CAN_F5R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3765 of file stm32f4xx.h.
| #define CAN_F5R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3774 of file stm32f4xx.h.
| #define CAN_F5R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3775 of file stm32f4xx.h.
| #define CAN_F5R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3776 of file stm32f4xx.h.
| #define CAN_F5R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3777 of file stm32f4xx.h.
| #define CAN_F5R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3778 of file stm32f4xx.h.
| #define CAN_F5R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3779 of file stm32f4xx.h.
| #define CAN_F5R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3780 of file stm32f4xx.h.
| #define CAN_F5R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3781 of file stm32f4xx.h.
| #define CAN_F5R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3782 of file stm32f4xx.h.
| #define CAN_F5R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3783 of file stm32f4xx.h.
| #define CAN_F5R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3766 of file stm32f4xx.h.
| #define CAN_F5R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3784 of file stm32f4xx.h.
| #define CAN_F5R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3785 of file stm32f4xx.h.
| #define CAN_F5R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3786 of file stm32f4xx.h.
| #define CAN_F5R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3787 of file stm32f4xx.h.
| #define CAN_F5R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3788 of file stm32f4xx.h.
| #define CAN_F5R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3789 of file stm32f4xx.h.
| #define CAN_F5R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3790 of file stm32f4xx.h.
| #define CAN_F5R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3791 of file stm32f4xx.h.
| #define CAN_F5R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3792 of file stm32f4xx.h.
| #define CAN_F5R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3793 of file stm32f4xx.h.
| #define CAN_F5R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3767 of file stm32f4xx.h.
| #define CAN_F5R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3794 of file stm32f4xx.h.
| #define CAN_F5R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3795 of file stm32f4xx.h.
| #define CAN_F5R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3768 of file stm32f4xx.h.
| #define CAN_F5R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3769 of file stm32f4xx.h.
| #define CAN_F5R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3770 of file stm32f4xx.h.
| #define CAN_F5R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3771 of file stm32f4xx.h.
| #define CAN_F5R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3772 of file stm32f4xx.h.
| #define CAN_F5R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3773 of file stm32f4xx.h.
| #define CAN_F6R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3322 of file stm32f4xx.h.
| #define CAN_F6R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3323 of file stm32f4xx.h.
| #define CAN_F6R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3332 of file stm32f4xx.h.
| #define CAN_F6R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3333 of file stm32f4xx.h.
| #define CAN_F6R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3334 of file stm32f4xx.h.
| #define CAN_F6R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3335 of file stm32f4xx.h.
| #define CAN_F6R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3336 of file stm32f4xx.h.
| #define CAN_F6R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3337 of file stm32f4xx.h.
| #define CAN_F6R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3338 of file stm32f4xx.h.
| #define CAN_F6R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3339 of file stm32f4xx.h.
| #define CAN_F6R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3340 of file stm32f4xx.h.
| #define CAN_F6R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3341 of file stm32f4xx.h.
| #define CAN_F6R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3324 of file stm32f4xx.h.
| #define CAN_F6R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3342 of file stm32f4xx.h.
| #define CAN_F6R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3343 of file stm32f4xx.h.
| #define CAN_F6R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3344 of file stm32f4xx.h.
| #define CAN_F6R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3345 of file stm32f4xx.h.
| #define CAN_F6R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3346 of file stm32f4xx.h.
| #define CAN_F6R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3347 of file stm32f4xx.h.
| #define CAN_F6R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3348 of file stm32f4xx.h.
| #define CAN_F6R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3349 of file stm32f4xx.h.
| #define CAN_F6R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3350 of file stm32f4xx.h.
| #define CAN_F6R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3351 of file stm32f4xx.h.
| #define CAN_F6R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3325 of file stm32f4xx.h.
| #define CAN_F6R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3352 of file stm32f4xx.h.
| #define CAN_F6R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3353 of file stm32f4xx.h.
| #define CAN_F6R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3326 of file stm32f4xx.h.
| #define CAN_F6R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3327 of file stm32f4xx.h.
| #define CAN_F6R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3328 of file stm32f4xx.h.
| #define CAN_F6R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3329 of file stm32f4xx.h.
| #define CAN_F6R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3330 of file stm32f4xx.h.
| #define CAN_F6R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3331 of file stm32f4xx.h.
| #define CAN_F6R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3798 of file stm32f4xx.h.
| #define CAN_F6R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3799 of file stm32f4xx.h.
| #define CAN_F6R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3808 of file stm32f4xx.h.
| #define CAN_F6R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3809 of file stm32f4xx.h.
| #define CAN_F6R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3810 of file stm32f4xx.h.
| #define CAN_F6R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3811 of file stm32f4xx.h.
| #define CAN_F6R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3812 of file stm32f4xx.h.
| #define CAN_F6R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3813 of file stm32f4xx.h.
| #define CAN_F6R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3814 of file stm32f4xx.h.
| #define CAN_F6R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3815 of file stm32f4xx.h.
| #define CAN_F6R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3816 of file stm32f4xx.h.
| #define CAN_F6R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3817 of file stm32f4xx.h.
| #define CAN_F6R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3800 of file stm32f4xx.h.
| #define CAN_F6R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3818 of file stm32f4xx.h.
| #define CAN_F6R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3819 of file stm32f4xx.h.
| #define CAN_F6R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3820 of file stm32f4xx.h.
| #define CAN_F6R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3821 of file stm32f4xx.h.
| #define CAN_F6R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3822 of file stm32f4xx.h.
| #define CAN_F6R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3823 of file stm32f4xx.h.
| #define CAN_F6R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3824 of file stm32f4xx.h.
| #define CAN_F6R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3825 of file stm32f4xx.h.
| #define CAN_F6R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3826 of file stm32f4xx.h.
| #define CAN_F6R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3827 of file stm32f4xx.h.
| #define CAN_F6R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3801 of file stm32f4xx.h.
| #define CAN_F6R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3828 of file stm32f4xx.h.
| #define CAN_F6R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3829 of file stm32f4xx.h.
| #define CAN_F6R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3802 of file stm32f4xx.h.
| #define CAN_F6R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3803 of file stm32f4xx.h.
| #define CAN_F6R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3804 of file stm32f4xx.h.
| #define CAN_F6R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3805 of file stm32f4xx.h.
| #define CAN_F6R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3806 of file stm32f4xx.h.
| #define CAN_F6R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3807 of file stm32f4xx.h.
| #define CAN_F7R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3356 of file stm32f4xx.h.
| #define CAN_F7R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3357 of file stm32f4xx.h.
| #define CAN_F7R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3366 of file stm32f4xx.h.
| #define CAN_F7R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3367 of file stm32f4xx.h.
| #define CAN_F7R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3368 of file stm32f4xx.h.
| #define CAN_F7R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3369 of file stm32f4xx.h.
| #define CAN_F7R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3370 of file stm32f4xx.h.
| #define CAN_F7R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3371 of file stm32f4xx.h.
| #define CAN_F7R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3372 of file stm32f4xx.h.
| #define CAN_F7R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3373 of file stm32f4xx.h.
| #define CAN_F7R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3374 of file stm32f4xx.h.
| #define CAN_F7R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3375 of file stm32f4xx.h.
| #define CAN_F7R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3358 of file stm32f4xx.h.
| #define CAN_F7R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3376 of file stm32f4xx.h.
| #define CAN_F7R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3377 of file stm32f4xx.h.
| #define CAN_F7R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3378 of file stm32f4xx.h.
| #define CAN_F7R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3379 of file stm32f4xx.h.
| #define CAN_F7R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3380 of file stm32f4xx.h.
| #define CAN_F7R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3381 of file stm32f4xx.h.
| #define CAN_F7R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3382 of file stm32f4xx.h.
| #define CAN_F7R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3383 of file stm32f4xx.h.
| #define CAN_F7R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3384 of file stm32f4xx.h.
| #define CAN_F7R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3385 of file stm32f4xx.h.
| #define CAN_F7R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3359 of file stm32f4xx.h.
| #define CAN_F7R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3386 of file stm32f4xx.h.
| #define CAN_F7R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3387 of file stm32f4xx.h.
| #define CAN_F7R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3360 of file stm32f4xx.h.
| #define CAN_F7R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3361 of file stm32f4xx.h.
| #define CAN_F7R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3362 of file stm32f4xx.h.
| #define CAN_F7R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3363 of file stm32f4xx.h.
| #define CAN_F7R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3364 of file stm32f4xx.h.
| #define CAN_F7R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3365 of file stm32f4xx.h.
| #define CAN_F7R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3832 of file stm32f4xx.h.
| #define CAN_F7R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3833 of file stm32f4xx.h.
| #define CAN_F7R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3842 of file stm32f4xx.h.
| #define CAN_F7R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3843 of file stm32f4xx.h.
| #define CAN_F7R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3844 of file stm32f4xx.h.
| #define CAN_F7R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3845 of file stm32f4xx.h.
| #define CAN_F7R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3846 of file stm32f4xx.h.
| #define CAN_F7R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3847 of file stm32f4xx.h.
| #define CAN_F7R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3848 of file stm32f4xx.h.
| #define CAN_F7R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3849 of file stm32f4xx.h.
| #define CAN_F7R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3850 of file stm32f4xx.h.
| #define CAN_F7R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3851 of file stm32f4xx.h.
| #define CAN_F7R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3834 of file stm32f4xx.h.
| #define CAN_F7R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3852 of file stm32f4xx.h.
| #define CAN_F7R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3853 of file stm32f4xx.h.
| #define CAN_F7R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3854 of file stm32f4xx.h.
| #define CAN_F7R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3855 of file stm32f4xx.h.
| #define CAN_F7R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3856 of file stm32f4xx.h.
| #define CAN_F7R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3857 of file stm32f4xx.h.
| #define CAN_F7R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3858 of file stm32f4xx.h.
| #define CAN_F7R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3859 of file stm32f4xx.h.
| #define CAN_F7R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3860 of file stm32f4xx.h.
| #define CAN_F7R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3861 of file stm32f4xx.h.
| #define CAN_F7R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3835 of file stm32f4xx.h.
| #define CAN_F7R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3862 of file stm32f4xx.h.
| #define CAN_F7R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3863 of file stm32f4xx.h.
| #define CAN_F7R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3836 of file stm32f4xx.h.
| #define CAN_F7R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3837 of file stm32f4xx.h.
| #define CAN_F7R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3838 of file stm32f4xx.h.
| #define CAN_F7R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3839 of file stm32f4xx.h.
| #define CAN_F7R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3840 of file stm32f4xx.h.
| #define CAN_F7R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3841 of file stm32f4xx.h.
| #define CAN_F8R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3390 of file stm32f4xx.h.
| #define CAN_F8R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3391 of file stm32f4xx.h.
| #define CAN_F8R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3400 of file stm32f4xx.h.
| #define CAN_F8R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3401 of file stm32f4xx.h.
| #define CAN_F8R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3402 of file stm32f4xx.h.
| #define CAN_F8R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3403 of file stm32f4xx.h.
| #define CAN_F8R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3404 of file stm32f4xx.h.
| #define CAN_F8R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3405 of file stm32f4xx.h.
| #define CAN_F8R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3406 of file stm32f4xx.h.
| #define CAN_F8R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3407 of file stm32f4xx.h.
| #define CAN_F8R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3408 of file stm32f4xx.h.
| #define CAN_F8R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3409 of file stm32f4xx.h.
| #define CAN_F8R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3392 of file stm32f4xx.h.
| #define CAN_F8R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3410 of file stm32f4xx.h.
| #define CAN_F8R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3411 of file stm32f4xx.h.
| #define CAN_F8R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3412 of file stm32f4xx.h.
| #define CAN_F8R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3413 of file stm32f4xx.h.
| #define CAN_F8R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3414 of file stm32f4xx.h.
| #define CAN_F8R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3415 of file stm32f4xx.h.
| #define CAN_F8R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3416 of file stm32f4xx.h.
| #define CAN_F8R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3417 of file stm32f4xx.h.
| #define CAN_F8R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3418 of file stm32f4xx.h.
| #define CAN_F8R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3419 of file stm32f4xx.h.
| #define CAN_F8R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3393 of file stm32f4xx.h.
| #define CAN_F8R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3420 of file stm32f4xx.h.
| #define CAN_F8R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3421 of file stm32f4xx.h.
| #define CAN_F8R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3394 of file stm32f4xx.h.
| #define CAN_F8R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3395 of file stm32f4xx.h.
| #define CAN_F8R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3396 of file stm32f4xx.h.
| #define CAN_F8R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3397 of file stm32f4xx.h.
| #define CAN_F8R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3398 of file stm32f4xx.h.
| #define CAN_F8R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3399 of file stm32f4xx.h.
| #define CAN_F8R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3866 of file stm32f4xx.h.
| #define CAN_F8R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3867 of file stm32f4xx.h.
| #define CAN_F8R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3876 of file stm32f4xx.h.
| #define CAN_F8R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3877 of file stm32f4xx.h.
| #define CAN_F8R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3878 of file stm32f4xx.h.
| #define CAN_F8R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3879 of file stm32f4xx.h.
| #define CAN_F8R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3880 of file stm32f4xx.h.
| #define CAN_F8R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3881 of file stm32f4xx.h.
| #define CAN_F8R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3882 of file stm32f4xx.h.
| #define CAN_F8R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3883 of file stm32f4xx.h.
| #define CAN_F8R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3884 of file stm32f4xx.h.
| #define CAN_F8R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3885 of file stm32f4xx.h.
| #define CAN_F8R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3868 of file stm32f4xx.h.
| #define CAN_F8R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3886 of file stm32f4xx.h.
| #define CAN_F8R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3887 of file stm32f4xx.h.
| #define CAN_F8R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3888 of file stm32f4xx.h.
| #define CAN_F8R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3889 of file stm32f4xx.h.
| #define CAN_F8R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3890 of file stm32f4xx.h.
| #define CAN_F8R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3891 of file stm32f4xx.h.
| #define CAN_F8R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3892 of file stm32f4xx.h.
| #define CAN_F8R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3893 of file stm32f4xx.h.
| #define CAN_F8R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3894 of file stm32f4xx.h.
| #define CAN_F8R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3895 of file stm32f4xx.h.
| #define CAN_F8R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3869 of file stm32f4xx.h.
| #define CAN_F8R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3896 of file stm32f4xx.h.
| #define CAN_F8R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3897 of file stm32f4xx.h.
| #define CAN_F8R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3870 of file stm32f4xx.h.
| #define CAN_F8R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3871 of file stm32f4xx.h.
| #define CAN_F8R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3872 of file stm32f4xx.h.
| #define CAN_F8R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3873 of file stm32f4xx.h.
| #define CAN_F8R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3874 of file stm32f4xx.h.
| #define CAN_F8R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3875 of file stm32f4xx.h.
| #define CAN_F9R1_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3424 of file stm32f4xx.h.
| #define CAN_F9R1_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3425 of file stm32f4xx.h.
| #define CAN_F9R1_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3434 of file stm32f4xx.h.
| #define CAN_F9R1_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3435 of file stm32f4xx.h.
| #define CAN_F9R1_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3436 of file stm32f4xx.h.
| #define CAN_F9R1_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3437 of file stm32f4xx.h.
| #define CAN_F9R1_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3438 of file stm32f4xx.h.
| #define CAN_F9R1_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3439 of file stm32f4xx.h.
| #define CAN_F9R1_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3440 of file stm32f4xx.h.
| #define CAN_F9R1_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3441 of file stm32f4xx.h.
| #define CAN_F9R1_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3442 of file stm32f4xx.h.
| #define CAN_F9R1_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3443 of file stm32f4xx.h.
| #define CAN_F9R1_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3426 of file stm32f4xx.h.
| #define CAN_F9R1_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3444 of file stm32f4xx.h.
| #define CAN_F9R1_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3445 of file stm32f4xx.h.
| #define CAN_F9R1_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3446 of file stm32f4xx.h.
| #define CAN_F9R1_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3447 of file stm32f4xx.h.
| #define CAN_F9R1_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3448 of file stm32f4xx.h.
| #define CAN_F9R1_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3449 of file stm32f4xx.h.
| #define CAN_F9R1_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3450 of file stm32f4xx.h.
| #define CAN_F9R1_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3451 of file stm32f4xx.h.
| #define CAN_F9R1_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3452 of file stm32f4xx.h.
| #define CAN_F9R1_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3453 of file stm32f4xx.h.
| #define CAN_F9R1_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3427 of file stm32f4xx.h.
| #define CAN_F9R1_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3454 of file stm32f4xx.h.
| #define CAN_F9R1_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3455 of file stm32f4xx.h.
| #define CAN_F9R1_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3428 of file stm32f4xx.h.
| #define CAN_F9R1_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3429 of file stm32f4xx.h.
| #define CAN_F9R1_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3430 of file stm32f4xx.h.
| #define CAN_F9R1_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3431 of file stm32f4xx.h.
| #define CAN_F9R1_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3432 of file stm32f4xx.h.
| #define CAN_F9R1_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3433 of file stm32f4xx.h.
| #define CAN_F9R2_FB0 ((uint32_t)0x00000001) |
Filter bit 0
Definition at line 3900 of file stm32f4xx.h.
| #define CAN_F9R2_FB1 ((uint32_t)0x00000002) |
Filter bit 1
Definition at line 3901 of file stm32f4xx.h.
| #define CAN_F9R2_FB10 ((uint32_t)0x00000400) |
Filter bit 10
Definition at line 3910 of file stm32f4xx.h.
| #define CAN_F9R2_FB11 ((uint32_t)0x00000800) |
Filter bit 11
Definition at line 3911 of file stm32f4xx.h.
| #define CAN_F9R2_FB12 ((uint32_t)0x00001000) |
Filter bit 12
Definition at line 3912 of file stm32f4xx.h.
| #define CAN_F9R2_FB13 ((uint32_t)0x00002000) |
Filter bit 13
Definition at line 3913 of file stm32f4xx.h.
| #define CAN_F9R2_FB14 ((uint32_t)0x00004000) |
Filter bit 14
Definition at line 3914 of file stm32f4xx.h.
| #define CAN_F9R2_FB15 ((uint32_t)0x00008000) |
Filter bit 15
Definition at line 3915 of file stm32f4xx.h.
| #define CAN_F9R2_FB16 ((uint32_t)0x00010000) |
Filter bit 16
Definition at line 3916 of file stm32f4xx.h.
| #define CAN_F9R2_FB17 ((uint32_t)0x00020000) |
Filter bit 17
Definition at line 3917 of file stm32f4xx.h.
| #define CAN_F9R2_FB18 ((uint32_t)0x00040000) |
Filter bit 18
Definition at line 3918 of file stm32f4xx.h.
| #define CAN_F9R2_FB19 ((uint32_t)0x00080000) |
Filter bit 19
Definition at line 3919 of file stm32f4xx.h.
| #define CAN_F9R2_FB2 ((uint32_t)0x00000004) |
Filter bit 2
Definition at line 3902 of file stm32f4xx.h.
| #define CAN_F9R2_FB20 ((uint32_t)0x00100000) |
Filter bit 20
Definition at line 3920 of file stm32f4xx.h.
| #define CAN_F9R2_FB21 ((uint32_t)0x00200000) |
Filter bit 21
Definition at line 3921 of file stm32f4xx.h.
| #define CAN_F9R2_FB22 ((uint32_t)0x00400000) |
Filter bit 22
Definition at line 3922 of file stm32f4xx.h.
| #define CAN_F9R2_FB23 ((uint32_t)0x00800000) |
Filter bit 23
Definition at line 3923 of file stm32f4xx.h.
| #define CAN_F9R2_FB24 ((uint32_t)0x01000000) |
Filter bit 24
Definition at line 3924 of file stm32f4xx.h.
| #define CAN_F9R2_FB25 ((uint32_t)0x02000000) |
Filter bit 25
Definition at line 3925 of file stm32f4xx.h.
| #define CAN_F9R2_FB26 ((uint32_t)0x04000000) |
Filter bit 26
Definition at line 3926 of file stm32f4xx.h.
| #define CAN_F9R2_FB27 ((uint32_t)0x08000000) |
Filter bit 27
Definition at line 3927 of file stm32f4xx.h.
| #define CAN_F9R2_FB28 ((uint32_t)0x10000000) |
Filter bit 28
Definition at line 3928 of file stm32f4xx.h.
| #define CAN_F9R2_FB29 ((uint32_t)0x20000000) |
Filter bit 29
Definition at line 3929 of file stm32f4xx.h.
| #define CAN_F9R2_FB3 ((uint32_t)0x00000008) |
Filter bit 3
Definition at line 3903 of file stm32f4xx.h.
| #define CAN_F9R2_FB30 ((uint32_t)0x40000000) |
Filter bit 30
Definition at line 3930 of file stm32f4xx.h.
| #define CAN_F9R2_FB31 ((uint32_t)0x80000000) |
Filter bit 31
Definition at line 3931 of file stm32f4xx.h.
| #define CAN_F9R2_FB4 ((uint32_t)0x00000010) |
Filter bit 4
Definition at line 3904 of file stm32f4xx.h.
| #define CAN_F9R2_FB5 ((uint32_t)0x00000020) |
Filter bit 5
Definition at line 3905 of file stm32f4xx.h.
| #define CAN_F9R2_FB6 ((uint32_t)0x00000040) |
Filter bit 6
Definition at line 3906 of file stm32f4xx.h.
| #define CAN_F9R2_FB7 ((uint32_t)0x00000080) |
Filter bit 7
Definition at line 3907 of file stm32f4xx.h.
| #define CAN_F9R2_FB8 ((uint32_t)0x00000100) |
Filter bit 8
Definition at line 3908 of file stm32f4xx.h.
| #define CAN_F9R2_FB9 ((uint32_t)0x00000200) |
Filter bit 9
Definition at line 3909 of file stm32f4xx.h.
| #define CAN_FA1R_FACT ((uint16_t)0x3FFF) |
Filter Active
Definition at line 3101 of file stm32f4xx.h.
| #define CAN_FA1R_FACT0 ((uint16_t)0x0001) |
Filter 0 Active
Definition at line 3102 of file stm32f4xx.h.
| #define CAN_FA1R_FACT1 ((uint16_t)0x0002) |
Filter 1 Active
Definition at line 3103 of file stm32f4xx.h.
| #define CAN_FA1R_FACT10 ((uint16_t)0x0400) |
Filter 10 Active
Definition at line 3112 of file stm32f4xx.h.
| #define CAN_FA1R_FACT11 ((uint16_t)0x0800) |
Filter 11 Active
Definition at line 3113 of file stm32f4xx.h.
| #define CAN_FA1R_FACT12 ((uint16_t)0x1000) |
Filter 12 Active
Definition at line 3114 of file stm32f4xx.h.
| #define CAN_FA1R_FACT13 ((uint16_t)0x2000) |
Filter 13 Active
Definition at line 3115 of file stm32f4xx.h.
| #define CAN_FA1R_FACT2 ((uint16_t)0x0004) |
Filter 2 Active
Definition at line 3104 of file stm32f4xx.h.
| #define CAN_FA1R_FACT3 ((uint16_t)0x0008) |
Filter 3 Active
Definition at line 3105 of file stm32f4xx.h.
| #define CAN_FA1R_FACT4 ((uint16_t)0x0010) |
Filter 4 Active
Definition at line 3106 of file stm32f4xx.h.
| #define CAN_FA1R_FACT5 ((uint16_t)0x0020) |
Filter 5 Active
Definition at line 3107 of file stm32f4xx.h.
| #define CAN_FA1R_FACT6 ((uint16_t)0x0040) |
Filter 6 Active
Definition at line 3108 of file stm32f4xx.h.
| #define CAN_FA1R_FACT7 ((uint16_t)0x0080) |
Filter 7 Active
Definition at line 3109 of file stm32f4xx.h.
| #define CAN_FA1R_FACT8 ((uint16_t)0x0100) |
Filter 8 Active
Definition at line 3110 of file stm32f4xx.h.
| #define CAN_FA1R_FACT9 ((uint16_t)0x0200) |
Filter 9 Active
Definition at line 3111 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) |
Filter FIFO Assignment
Definition at line 3084 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) |
Filter FIFO Assignment for Filter 0
Definition at line 3085 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) |
Filter FIFO Assignment for Filter 1
Definition at line 3086 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) |
Filter FIFO Assignment for Filter 10
Definition at line 3095 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) |
Filter FIFO Assignment for Filter 11
Definition at line 3096 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) |
Filter FIFO Assignment for Filter 12
Definition at line 3097 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) |
Filter FIFO Assignment for Filter 13
Definition at line 3098 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) |
Filter FIFO Assignment for Filter 2
Definition at line 3087 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) |
Filter FIFO Assignment for Filter 3
Definition at line 3088 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) |
Filter FIFO Assignment for Filter 4
Definition at line 3089 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) |
Filter FIFO Assignment for Filter 5
Definition at line 3090 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) |
Filter FIFO Assignment for Filter 6
Definition at line 3091 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) |
Filter FIFO Assignment for Filter 7
Definition at line 3092 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) |
Filter FIFO Assignment for Filter 8
Definition at line 3093 of file stm32f4xx.h.
| #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) |
Filter FIFO Assignment for Filter 9
Definition at line 3094 of file stm32f4xx.h.
| #define CAN_FM1R_FBM ((uint16_t)0x3FFF) |
Filter Mode
Definition at line 3050 of file stm32f4xx.h.
| #define CAN_FM1R_FBM0 ((uint16_t)0x0001) |
Filter Init Mode bit 0
Definition at line 3051 of file stm32f4xx.h.
| #define CAN_FM1R_FBM1 ((uint16_t)0x0002) |
Filter Init Mode bit 1
Definition at line 3052 of file stm32f4xx.h.
| #define CAN_FM1R_FBM10 ((uint16_t)0x0400) |
Filter Init Mode bit 10
Definition at line 3061 of file stm32f4xx.h.
| #define CAN_FM1R_FBM11 ((uint16_t)0x0800) |
Filter Init Mode bit 11
Definition at line 3062 of file stm32f4xx.h.
| #define CAN_FM1R_FBM12 ((uint16_t)0x1000) |
Filter Init Mode bit 12
Definition at line 3063 of file stm32f4xx.h.
| #define CAN_FM1R_FBM13 ((uint16_t)0x2000) |
Filter Init Mode bit 13
Definition at line 3064 of file stm32f4xx.h.
| #define CAN_FM1R_FBM2 ((uint16_t)0x0004) |
Filter Init Mode bit 2
Definition at line 3053 of file stm32f4xx.h.
| #define CAN_FM1R_FBM3 ((uint16_t)0x0008) |
Filter Init Mode bit 3
Definition at line 3054 of file stm32f4xx.h.
| #define CAN_FM1R_FBM4 ((uint16_t)0x0010) |
Filter Init Mode bit 4
Definition at line 3055 of file stm32f4xx.h.
| #define CAN_FM1R_FBM5 ((uint16_t)0x0020) |
Filter Init Mode bit 5
Definition at line 3056 of file stm32f4xx.h.
| #define CAN_FM1R_FBM6 ((uint16_t)0x0040) |
Filter Init Mode bit 6
Definition at line 3057 of file stm32f4xx.h.
| #define CAN_FM1R_FBM7 ((uint16_t)0x0080) |
Filter Init Mode bit 7
Definition at line 3058 of file stm32f4xx.h.
| #define CAN_FM1R_FBM8 ((uint16_t)0x0100) |
Filter Init Mode bit 8
Definition at line 3059 of file stm32f4xx.h.
| #define CAN_FM1R_FBM9 ((uint16_t)0x0200) |
Filter Init Mode bit 9
Definition at line 3060 of file stm32f4xx.h.
| #define CAN_FMR_FINIT ((uint8_t)0x01) |
Filter Init Mode
Definition at line 3047 of file stm32f4xx.h.
| #define CAN_FS1R_FSC ((uint16_t)0x3FFF) |
Filter Scale Configuration
Definition at line 3067 of file stm32f4xx.h.
| #define CAN_FS1R_FSC0 ((uint16_t)0x0001) |
Filter Scale Configuration bit 0
Definition at line 3068 of file stm32f4xx.h.
| #define CAN_FS1R_FSC1 ((uint16_t)0x0002) |
Filter Scale Configuration bit 1
Definition at line 3069 of file stm32f4xx.h.
| #define CAN_FS1R_FSC10 ((uint16_t)0x0400) |
Filter Scale Configuration bit 10
Definition at line 3078 of file stm32f4xx.h.
| #define CAN_FS1R_FSC11 ((uint16_t)0x0800) |
Filter Scale Configuration bit 11
Definition at line 3079 of file stm32f4xx.h.
| #define CAN_FS1R_FSC12 ((uint16_t)0x1000) |
Filter Scale Configuration bit 12
Definition at line 3080 of file stm32f4xx.h.
| #define CAN_FS1R_FSC13 ((uint16_t)0x2000) |
Filter Scale Configuration bit 13
Definition at line 3081 of file stm32f4xx.h.
| #define CAN_FS1R_FSC2 ((uint16_t)0x0004) |
Filter Scale Configuration bit 2
Definition at line 3070 of file stm32f4xx.h.
| #define CAN_FS1R_FSC3 ((uint16_t)0x0008) |
Filter Scale Configuration bit 3
Definition at line 3071 of file stm32f4xx.h.
| #define CAN_FS1R_FSC4 ((uint16_t)0x0010) |
Filter Scale Configuration bit 4
Definition at line 3072 of file stm32f4xx.h.
| #define CAN_FS1R_FSC5 ((uint16_t)0x0020) |
Filter Scale Configuration bit 5
Definition at line 3073 of file stm32f4xx.h.
| #define CAN_FS1R_FSC6 ((uint16_t)0x0040) |
Filter Scale Configuration bit 6
Definition at line 3074 of file stm32f4xx.h.
| #define CAN_FS1R_FSC7 ((uint16_t)0x0080) |
Filter Scale Configuration bit 7
Definition at line 3075 of file stm32f4xx.h.
| #define CAN_FS1R_FSC8 ((uint16_t)0x0100) |
Filter Scale Configuration bit 8
Definition at line 3076 of file stm32f4xx.h.
| #define CAN_FS1R_FSC9 ((uint16_t)0x0200) |
Filter Scale Configuration bit 9
Definition at line 3077 of file stm32f4xx.h.
| #define CAN_IER_BOFIE ((uint32_t)0x00000400) |
Bus-Off Interrupt Enable
Definition at line 2899 of file stm32f4xx.h.
| #define CAN_IER_EPVIE ((uint32_t)0x00000200) |
Error Passive Interrupt Enable
Definition at line 2898 of file stm32f4xx.h.
| #define CAN_IER_ERRIE ((uint32_t)0x00008000) |
Error Interrupt Enable
Definition at line 2901 of file stm32f4xx.h.
| #define CAN_IER_EWGIE ((uint32_t)0x00000100) |
Error Warning Interrupt Enable
Definition at line 2897 of file stm32f4xx.h.
| #define CAN_IER_FFIE0 ((uint32_t)0x00000004) |
FIFO Full Interrupt Enable
Definition at line 2892 of file stm32f4xx.h.
| #define CAN_IER_FFIE1 ((uint32_t)0x00000020) |
FIFO Full Interrupt Enable
Definition at line 2895 of file stm32f4xx.h.
| #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
FIFO Message Pending Interrupt Enable
Definition at line 2891 of file stm32f4xx.h.
| #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
FIFO Message Pending Interrupt Enable
Definition at line 2894 of file stm32f4xx.h.
| #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
FIFO Overrun Interrupt Enable
Definition at line 2893 of file stm32f4xx.h.
| #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
FIFO Overrun Interrupt Enable
Definition at line 2896 of file stm32f4xx.h.
| #define CAN_IER_LECIE ((uint32_t)0x00000800) |
Last Error Code Interrupt Enable
Definition at line 2900 of file stm32f4xx.h.
| #define CAN_IER_SLKIE ((uint32_t)0x00020000) |
Sleep Interrupt Enable
Definition at line 2903 of file stm32f4xx.h.
| #define CAN_IER_TMEIE ((uint32_t)0x00000001) |
Transmit Mailbox Empty Interrupt Enable
Definition at line 2890 of file stm32f4xx.h.
| #define CAN_IER_WKUIE ((uint32_t)0x00010000) |
Wakeup Interrupt Enable
Definition at line 2902 of file stm32f4xx.h.
| #define CAN_MCR_ABOM ((uint16_t)0x0040) |
| #define CAN_MCR_AWUM ((uint16_t)0x0020) |
| #define CAN_MCR_INRQ ((uint16_t)0x0001) |
<CAN control and status registers Initialization Request
Definition at line 2828 of file stm32f4xx.h.
Referenced by CAN_Init(), CAN_OperatingModeRequest(), and CAN_Sleep().
| #define CAN_MCR_NART ((uint16_t)0x0010) |
| #define CAN_MCR_RESET ((uint16_t)0x8000) |
bxCAN software master reset
Definition at line 2836 of file stm32f4xx.h.
| #define CAN_MCR_RFLM ((uint16_t)0x0008) |
| #define CAN_MCR_SLEEP ((uint16_t)0x0002) |
Sleep Mode Request
Definition at line 2829 of file stm32f4xx.h.
Referenced by CAN_Init(), CAN_OperatingModeRequest(), CAN_Sleep(), and CAN_WakeUp().
| #define CAN_MCR_TTCM ((uint16_t)0x0080) |
Time Triggered Communication Mode
Definition at line 2835 of file stm32f4xx.h.
Referenced by CAN_Init(), and CAN_TTComModeCmd().
| #define CAN_MCR_TXFP ((uint16_t)0x0004) |
| #define CAN_MSR_ERRI ((uint16_t)0x0004) |
Error Interrupt
Definition at line 2841 of file stm32f4xx.h.
Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().
| #define CAN_MSR_INAK ((uint16_t)0x0001) |
Initialization Acknowledge
Definition at line 2839 of file stm32f4xx.h.
Referenced by CAN_Init(), CAN_OperatingModeRequest(), and CAN_Sleep().
| #define CAN_MSR_RX ((uint16_t)0x0800) |
CAN Rx Signal
Definition at line 2847 of file stm32f4xx.h.
| #define CAN_MSR_RXM ((uint16_t)0x0200) |
Receive Mode
Definition at line 2845 of file stm32f4xx.h.
| #define CAN_MSR_SAMP ((uint16_t)0x0400) |
Last Sample Point
Definition at line 2846 of file stm32f4xx.h.
| #define CAN_MSR_SLAK ((uint16_t)0x0002) |
Sleep Acknowledge
Definition at line 2840 of file stm32f4xx.h.
Referenced by CAN_OperatingModeRequest(), CAN_Sleep(), and CAN_WakeUp().
| #define CAN_MSR_SLAKI ((uint16_t)0x0010) |
Sleep Acknowledge Interrupt
Definition at line 2843 of file stm32f4xx.h.
Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().
| #define CAN_MSR_TXM ((uint16_t)0x0100) |
Transmit Mode
Definition at line 2844 of file stm32f4xx.h.
| #define CAN_MSR_WKUI ((uint16_t)0x0008) |
Wakeup Interrupt
Definition at line 2842 of file stm32f4xx.h.
Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().
| #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
Data byte 4
Definition at line 3017 of file stm32f4xx.h.
| #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
Data byte 5
Definition at line 3018 of file stm32f4xx.h.
| #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
Data byte 6
Definition at line 3019 of file stm32f4xx.h.
| #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
Data byte 7
Definition at line 3020 of file stm32f4xx.h.
| #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
Data byte 4
Definition at line 3040 of file stm32f4xx.h.
| #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
Data byte 5
Definition at line 3041 of file stm32f4xx.h.
| #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
Data byte 6
Definition at line 3042 of file stm32f4xx.h.
| #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
Data byte 7 CAN filter registers
Definition at line 3043 of file stm32f4xx.h.
| #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
Data byte 0
Definition at line 3011 of file stm32f4xx.h.
| #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
Data byte 1
Definition at line 3012 of file stm32f4xx.h.
| #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
Data byte 2
Definition at line 3013 of file stm32f4xx.h.
| #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
Data byte 3
Definition at line 3014 of file stm32f4xx.h.
| #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
Data byte 0
Definition at line 3034 of file stm32f4xx.h.
| #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
Data byte 1
Definition at line 3035 of file stm32f4xx.h.
| #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
Data byte 2
Definition at line 3036 of file stm32f4xx.h.
| #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
Data byte 3
Definition at line 3037 of file stm32f4xx.h.
| #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
Data Length Code
Definition at line 3006 of file stm32f4xx.h.
| #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
Filter Match Index
Definition at line 3007 of file stm32f4xx.h.
| #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
Message Time Stamp
Definition at line 3008 of file stm32f4xx.h.
| #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
Data Length Code
Definition at line 3029 of file stm32f4xx.h.
| #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
Filter Match Index
Definition at line 3030 of file stm32f4xx.h.
| #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
Message Time Stamp
Definition at line 3031 of file stm32f4xx.h.
| #define CAN_RF0R_FMP0 ((uint8_t)0x03) |
FIFO 0 Message Pending
Definition at line 2878 of file stm32f4xx.h.
Referenced by CAN_GetITStatus().
| #define CAN_RF0R_FOVR0 ((uint8_t)0x10) |
FIFO 0 Overrun
Definition at line 2880 of file stm32f4xx.h.
Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().
| #define CAN_RF0R_FULL0 ((uint8_t)0x08) |
FIFO 0 Full
Definition at line 2879 of file stm32f4xx.h.
Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().
| #define CAN_RF0R_RFOM0 ((uint8_t)0x20) |
Release FIFO 0 Output Mailbox
Definition at line 2881 of file stm32f4xx.h.
Referenced by CAN_FIFORelease(), and CAN_Receive().
| #define CAN_RF1R_FMP1 ((uint8_t)0x03) |
FIFO 1 Message Pending
Definition at line 2884 of file stm32f4xx.h.
Referenced by CAN_GetITStatus().
| #define CAN_RF1R_FOVR1 ((uint8_t)0x10) |
FIFO 1 Overrun
Definition at line 2886 of file stm32f4xx.h.
Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().
| #define CAN_RF1R_FULL1 ((uint8_t)0x08) |
FIFO 1 Full
Definition at line 2885 of file stm32f4xx.h.
Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().
| #define CAN_RF1R_RFOM1 ((uint8_t)0x20) |
Release FIFO 1 Output Mailbox
Definition at line 2887 of file stm32f4xx.h.
Referenced by CAN_FIFORelease(), and CAN_Receive().
| #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
Extended Identifier
Definition at line 3002 of file stm32f4xx.h.
| #define CAN_RI0R_IDE ((uint32_t)0x00000004) |
Identifier Extension
Definition at line 3001 of file stm32f4xx.h.
| #define CAN_RI0R_RTR ((uint32_t)0x00000002) |
Remote Transmission Request
Definition at line 3000 of file stm32f4xx.h.
| #define CAN_RI0R_STID ((uint32_t)0xFFE00000) |
Standard Identifier or Extended Identifier
Definition at line 3003 of file stm32f4xx.h.
| #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
Extended identifier
Definition at line 3025 of file stm32f4xx.h.
| #define CAN_RI1R_IDE ((uint32_t)0x00000004) |
Identifier Extension
Definition at line 3024 of file stm32f4xx.h.
| #define CAN_RI1R_RTR ((uint32_t)0x00000002) |
Remote Transmission Request
Definition at line 3023 of file stm32f4xx.h.
| #define CAN_RI1R_STID ((uint32_t)0xFFE00000) |
Standard Identifier or Extended Identifier
Definition at line 3026 of file stm32f4xx.h.
| #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
Data byte 4
Definition at line 2946 of file stm32f4xx.h.
| #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
Data byte 5
Definition at line 2947 of file stm32f4xx.h.
| #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
Data byte 6
Definition at line 2948 of file stm32f4xx.h.
| #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
Data byte 7
Definition at line 2949 of file stm32f4xx.h.
| #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
Data byte 4
Definition at line 2970 of file stm32f4xx.h.
| #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
Data byte 5
Definition at line 2971 of file stm32f4xx.h.
| #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
Data byte 6
Definition at line 2972 of file stm32f4xx.h.
| #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
Data byte 7
Definition at line 2973 of file stm32f4xx.h.
| #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
Data byte 4
Definition at line 2994 of file stm32f4xx.h.
| #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
Data byte 5
Definition at line 2995 of file stm32f4xx.h.
| #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
Data byte 6
Definition at line 2996 of file stm32f4xx.h.
| #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
Data byte 7
Definition at line 2997 of file stm32f4xx.h.
| #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
Data byte 0
Definition at line 2940 of file stm32f4xx.h.
| #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
Data byte 1
Definition at line 2941 of file stm32f4xx.h.
| #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
Data byte 2
Definition at line 2942 of file stm32f4xx.h.
| #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
Data byte 3
Definition at line 2943 of file stm32f4xx.h.
| #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
Data byte 0
Definition at line 2964 of file stm32f4xx.h.
| #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
Data byte 1
Definition at line 2965 of file stm32f4xx.h.
| #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
Data byte 2
Definition at line 2966 of file stm32f4xx.h.
| #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
Data byte 3
Definition at line 2967 of file stm32f4xx.h.
| #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
Data byte 0
Definition at line 2988 of file stm32f4xx.h.
| #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
Data byte 1
Definition at line 2989 of file stm32f4xx.h.
| #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
Data byte 2
Definition at line 2990 of file stm32f4xx.h.
| #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
Data byte 3
Definition at line 2991 of file stm32f4xx.h.
| #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
Data Length Code
Definition at line 2935 of file stm32f4xx.h.
| #define CAN_TDT0R_TGT ((uint32_t)0x00000100) |
| #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
Message Time Stamp
Definition at line 2937 of file stm32f4xx.h.
| #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
Data Length Code
Definition at line 2959 of file stm32f4xx.h.
| #define CAN_TDT1R_TGT ((uint32_t)0x00000100) |
| #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
Message Time Stamp
Definition at line 2961 of file stm32f4xx.h.
| #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
Data Length Code
Definition at line 2983 of file stm32f4xx.h.
| #define CAN_TDT2R_TGT ((uint32_t)0x00000100) |
| #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
Message Time Stamp
Definition at line 2985 of file stm32f4xx.h.
| #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
Extended Identifier
Definition at line 2931 of file stm32f4xx.h.
| #define CAN_TI0R_IDE ((uint32_t)0x00000004) |
Identifier Extension
Definition at line 2930 of file stm32f4xx.h.
| #define CAN_TI0R_RTR ((uint32_t)0x00000002) |
Remote Transmission Request
Definition at line 2929 of file stm32f4xx.h.
| #define CAN_TI0R_STID ((uint32_t)0xFFE00000) |
Standard Identifier or Extended Identifier
Definition at line 2932 of file stm32f4xx.h.
| #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
Transmit Mailbox Request
Definition at line 2928 of file stm32f4xx.h.
| #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
Extended Identifier
Definition at line 2955 of file stm32f4xx.h.
| #define CAN_TI1R_IDE ((uint32_t)0x00000004) |
Identifier Extension
Definition at line 2954 of file stm32f4xx.h.
| #define CAN_TI1R_RTR ((uint32_t)0x00000002) |
Remote Transmission Request
Definition at line 2953 of file stm32f4xx.h.
| #define CAN_TI1R_STID ((uint32_t)0xFFE00000) |
Standard Identifier or Extended Identifier
Definition at line 2956 of file stm32f4xx.h.
| #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
Transmit Mailbox Request
Definition at line 2952 of file stm32f4xx.h.
| #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
Extended identifier
Definition at line 2979 of file stm32f4xx.h.
| #define CAN_TI2R_IDE ((uint32_t)0x00000004) |
Identifier Extension
Definition at line 2978 of file stm32f4xx.h.
| #define CAN_TI2R_RTR ((uint32_t)0x00000002) |
Remote Transmission Request
Definition at line 2977 of file stm32f4xx.h.
| #define CAN_TI2R_STID ((uint32_t)0xFFE00000) |
Standard Identifier or Extended Identifier
Definition at line 2980 of file stm32f4xx.h.
| #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
Transmit Mailbox Request
Definition at line 2976 of file stm32f4xx.h.
| #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
Abort Request for Mailbox0
Definition at line 2854 of file stm32f4xx.h.
Referenced by CAN_CancelTransmit().
| #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
Abort Request for Mailbox 1
Definition at line 2859 of file stm32f4xx.h.
Referenced by CAN_CancelTransmit().
| #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
Abort Request for Mailbox 2
Definition at line 2864 of file stm32f4xx.h.
Referenced by CAN_CancelTransmit().
| #define CAN_TSR_ALST0 ((uint32_t)0x00000004) |
Arbitration Lost for Mailbox0
Definition at line 2852 of file stm32f4xx.h.
| #define CAN_TSR_ALST1 ((uint32_t)0x00000400) |
Arbitration Lost for Mailbox1
Definition at line 2857 of file stm32f4xx.h.
| #define CAN_TSR_ALST2 ((uint32_t)0x00040000) |
Arbitration Lost for mailbox 2
Definition at line 2862 of file stm32f4xx.h.
| #define CAN_TSR_CODE ((uint32_t)0x03000000) |
Mailbox Code
Definition at line 2865 of file stm32f4xx.h.
| #define CAN_TSR_LOW ((uint32_t)0xE0000000) |
LOW[2:0] bits
Definition at line 2872 of file stm32f4xx.h.
| #define CAN_TSR_LOW0 ((uint32_t)0x20000000) |
Lowest Priority Flag for Mailbox 0
Definition at line 2873 of file stm32f4xx.h.
| #define CAN_TSR_LOW1 ((uint32_t)0x40000000) |
Lowest Priority Flag for Mailbox 1
Definition at line 2874 of file stm32f4xx.h.
| #define CAN_TSR_LOW2 ((uint32_t)0x80000000) |
Lowest Priority Flag for Mailbox 2
Definition at line 2875 of file stm32f4xx.h.
| #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
Request Completed Mailbox0
Definition at line 2850 of file stm32f4xx.h.
Referenced by CAN_ClearITPendingBit(), CAN_GetITStatus(), and CAN_TransmitStatus().
| #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
Request Completed Mailbox1
Definition at line 2855 of file stm32f4xx.h.
Referenced by CAN_ClearITPendingBit(), CAN_GetITStatus(), and CAN_TransmitStatus().
| #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
Request Completed Mailbox2
Definition at line 2860 of file stm32f4xx.h.
Referenced by CAN_ClearITPendingBit(), CAN_GetITStatus(), and CAN_TransmitStatus().
| #define CAN_TSR_TERR0 ((uint32_t)0x00000008) |
Transmission Error of Mailbox0
Definition at line 2853 of file stm32f4xx.h.
| #define CAN_TSR_TERR1 ((uint32_t)0x00000800) |
Transmission Error of Mailbox1
Definition at line 2858 of file stm32f4xx.h.
| #define CAN_TSR_TERR2 ((uint32_t)0x00080000) |
Transmission Error of Mailbox 2
Definition at line 2863 of file stm32f4xx.h.
| #define CAN_TSR_TME ((uint32_t)0x1C000000) |
TME[2:0] bits
Definition at line 2867 of file stm32f4xx.h.
| #define CAN_TSR_TME0 ((uint32_t)0x04000000) |
Transmit Mailbox 0 Empty
Definition at line 2868 of file stm32f4xx.h.
Referenced by CAN_Transmit(), and CAN_TransmitStatus().
| #define CAN_TSR_TME1 ((uint32_t)0x08000000) |
Transmit Mailbox 1 Empty
Definition at line 2869 of file stm32f4xx.h.
Referenced by CAN_Transmit(), and CAN_TransmitStatus().
| #define CAN_TSR_TME2 ((uint32_t)0x10000000) |
Transmit Mailbox 2 Empty
Definition at line 2870 of file stm32f4xx.h.
Referenced by CAN_Transmit(), and CAN_TransmitStatus().
| #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
Transmission OK of Mailbox0
Definition at line 2851 of file stm32f4xx.h.
Referenced by CAN_TransmitStatus().
| #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
Transmission OK of Mailbox1
Definition at line 2856 of file stm32f4xx.h.
Referenced by CAN_TransmitStatus().
| #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
Transmission OK of Mailbox 2
Definition at line 2861 of file stm32f4xx.h.
Referenced by CAN_TransmitStatus().
| #define CRC_CR_RESET ((uint8_t)0x01) |
| #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
Data register bits
Definition at line 4135 of file stm32f4xx.h.
| #define CRC_IDR_IDR ((uint8_t)0xFF) |
General-purpose 8-bit data register bits
Definition at line 4139 of file stm32f4xx.h.
| #define CRYP_CR_ALGODIR ((uint32_t)0x00000004) |
Definition at line 4151 of file stm32f4xx.h.
Referenced by CRYP_SaveContext().
| #define CRYP_CR_ALGOMODE ((uint32_t)0x00080038) |
Definition at line 4153 of file stm32f4xx.h.
Referenced by CRYP_SaveContext().
| #define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008) |
Definition at line 4154 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010) |
Definition at line 4155 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020) |
Definition at line 4156 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) |
Definition at line 4178 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028) |
Definition at line 4162 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030) |
Definition at line 4163 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020) |
Definition at line 4161 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038) |
Definition at line 4164 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018) |
Definition at line 4160 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010) |
Definition at line 4159 of file stm32f4xx.h.
| #define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008) |
Definition at line 4158 of file stm32f4xx.h.
Referenced by CRYP_SaveContext().
| #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) |
Definition at line 4157 of file stm32f4xx.h.
Referenced by CRYP_SaveContext().
| #define CRYP_CR_CRYPEN ((uint32_t)0x00008000) |
Definition at line 4173 of file stm32f4xx.h.
Referenced by CRYP_Cmd(), CRYP_GetCmdStatus(), CRYP_RestoreContext(), and CRYP_SaveContext().
| #define CRYP_CR_DATATYPE ((uint32_t)0x000000C0) |
Definition at line 4166 of file stm32f4xx.h.
Referenced by CRYP_SaveContext().
| #define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040) |
Definition at line 4167 of file stm32f4xx.h.
| #define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080) |
Definition at line 4168 of file stm32f4xx.h.
| #define CRYP_CR_FFLUSH ((uint32_t)0x00004000) |
Definition at line 4172 of file stm32f4xx.h.
Referenced by CRYP_FIFOFlush().
| #define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000) |
Definition at line 4175 of file stm32f4xx.h.
Referenced by CRYP_PhaseConfig(), and CRYP_SaveContext().
| #define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000) |
Definition at line 4176 of file stm32f4xx.h.
| #define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000) |
Definition at line 4177 of file stm32f4xx.h.
| #define CRYP_CR_KEYSIZE ((uint32_t)0x00000300) |
Definition at line 4169 of file stm32f4xx.h.
Referenced by CRYP_SaveContext().
| #define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100) |
Definition at line 4170 of file stm32f4xx.h.
| #define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200) |
Definition at line 4171 of file stm32f4xx.h.
| #define CRYP_DMACR_DIEN ((uint32_t)0x00000001) |
Definition at line 4187 of file stm32f4xx.h.
Referenced by CRYP_SaveContext().
| #define CRYP_DMACR_DOEN ((uint32_t)0x00000002) |
Definition at line 4188 of file stm32f4xx.h.
Referenced by CRYP_SaveContext().
| #define CRYP_IMSCR_INIM ((uint32_t)0x00000001) |
Definition at line 4190 of file stm32f4xx.h.
| #define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002) |
Definition at line 4191 of file stm32f4xx.h.
| #define CRYP_MISR_INMIS ((uint32_t)0x00000001) |
Definition at line 4196 of file stm32f4xx.h.
| #define CRYP_MISR_OUTMIS ((uint32_t)0x00000002) |
Definition at line 4197 of file stm32f4xx.h.
| #define CRYP_RISR_INRIS ((uint32_t)0x00000002) |
Definition at line 4194 of file stm32f4xx.h.
| #define CRYP_RISR_OUTRIS ((uint32_t)0x00000001) |
Definition at line 4193 of file stm32f4xx.h.
| #define CRYP_SR_BUSY ((uint32_t)0x00000010) |
Definition at line 4185 of file stm32f4xx.h.
Referenced by CRYP_SaveContext().
| #define CRYP_SR_IFEM ((uint32_t)0x00000001) |
Definition at line 4181 of file stm32f4xx.h.
Referenced by CRYP_SaveContext().
| #define CRYP_SR_IFNF ((uint32_t)0x00000002) |
Definition at line 4182 of file stm32f4xx.h.
| #define CRYP_SR_OFFU ((uint32_t)0x00000008) |
Definition at line 4184 of file stm32f4xx.h.
| #define CRYP_SR_OFNE ((uint32_t)0x00000004) |
Definition at line 4183 of file stm32f4xx.h.
Referenced by CRYP_SaveContext().
| #define DAC_CR_BOFF1 ((uint32_t)0x00000002) |
DAC channel1 output buffer disable
Definition at line 4206 of file stm32f4xx.h.
| #define DAC_CR_BOFF2 ((uint32_t)0x00020000) |
DAC channel2 output buffer disable
Definition at line 4227 of file stm32f4xx.h.
| #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
DAC channel2 DMA enabled
Definition at line 4245 of file stm32f4xx.h.
| #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) |
DAC channel1 DMA underrun interrupt enable
Definition at line 4225 of file stm32f4xx.h.
| #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000U) |
DAC channel2 DMA underrun interrupt enable
Definition at line 4246 of file stm32f4xx.h.
| #define DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define DAC_CR_EN2 ((uint32_t)0x00010000) |
DAC channel2 enable
Definition at line 4226 of file stm32f4xx.h.
| #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
Definition at line 4218 of file stm32f4xx.h.
| #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 4219 of file stm32f4xx.h.
| #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 4220 of file stm32f4xx.h.
| #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 4221 of file stm32f4xx.h.
| #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 4222 of file stm32f4xx.h.
| #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)
Definition at line 4239 of file stm32f4xx.h.
| #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
Bit 0
Definition at line 4240 of file stm32f4xx.h.
| #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
Bit 1
Definition at line 4241 of file stm32f4xx.h.
| #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
Bit 2
Definition at line 4242 of file stm32f4xx.h.
| #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
Bit 3
Definition at line 4243 of file stm32f4xx.h.
| #define DAC_CR_TEN1 ((uint32_t)0x00000004) |
DAC channel1 Trigger enable
Definition at line 4207 of file stm32f4xx.h.
| #define DAC_CR_TEN2 ((uint32_t)0x00040000) |
DAC channel2 Trigger enable
Definition at line 4228 of file stm32f4xx.h.
| #define DAC_CR_TSEL1 ((uint32_t)0x00000038) |
TSEL1[2:0] (DAC channel1 Trigger selection)
Definition at line 4209 of file stm32f4xx.h.
| #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
Bit 0
Definition at line 4210 of file stm32f4xx.h.
| #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
Bit 1
Definition at line 4211 of file stm32f4xx.h.
| #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
Bit 2
Definition at line 4212 of file stm32f4xx.h.
| #define DAC_CR_TSEL2 ((uint32_t)0x00380000) |
TSEL2[2:0] (DAC channel2 Trigger selection)
Definition at line 4230 of file stm32f4xx.h.
| #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
Bit 0
Definition at line 4231 of file stm32f4xx.h.
| #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
Bit 1
Definition at line 4232 of file stm32f4xx.h.
| #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
Bit 2
Definition at line 4233 of file stm32f4xx.h.
| #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
Definition at line 4214 of file stm32f4xx.h.
| #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
Bit 0
Definition at line 4215 of file stm32f4xx.h.
| #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
Bit 1
Definition at line 4216 of file stm32f4xx.h.
| #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)
Definition at line 4235 of file stm32f4xx.h.
| #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
Bit 0
Definition at line 4236 of file stm32f4xx.h.
| #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
Bit 1
Definition at line 4237 of file stm32f4xx.h.
| #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) |
DAC channel1 12-bit Left aligned data
Definition at line 4256 of file stm32f4xx.h.
| #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) |
DAC channel2 12-bit Left aligned data
Definition at line 4265 of file stm32f4xx.h.
| #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
DAC channel1 12-bit Left aligned data
Definition at line 4275 of file stm32f4xx.h.
| #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
DAC channel2 12-bit Left aligned data
Definition at line 4276 of file stm32f4xx.h.
| #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) |
DAC channel1 12-bit Right aligned data
Definition at line 4253 of file stm32f4xx.h.
| #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) |
DAC channel2 12-bit Right aligned data
Definition at line 4262 of file stm32f4xx.h.
| #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
DAC channel1 12-bit Right aligned data
Definition at line 4271 of file stm32f4xx.h.
| #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
DAC channel2 12-bit Right aligned data
Definition at line 4272 of file stm32f4xx.h.
| #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) |
DAC channel1 8-bit Right aligned data
Definition at line 4259 of file stm32f4xx.h.
| #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) |
DAC channel2 8-bit Right aligned data
Definition at line 4268 of file stm32f4xx.h.
| #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) |
DAC channel1 8-bit Right aligned data
Definition at line 4279 of file stm32f4xx.h.
| #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) |
DAC channel2 8-bit Right aligned data
Definition at line 4280 of file stm32f4xx.h.
| #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) |
DAC channel1 data output
Definition at line 4283 of file stm32f4xx.h.
| #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) |
DAC channel2 data output
Definition at line 4286 of file stm32f4xx.h.
| #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) |
DAC channel1 DMA underrun flag
Definition at line 4289 of file stm32f4xx.h.
| #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) |
DAC channel2 DMA underrun flag
Definition at line 4290 of file stm32f4xx.h.
| #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) |
DAC channel1 software trigger
Definition at line 4249 of file stm32f4xx.h.
Referenced by DAC_SoftwareTriggerCmd().
| #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) |
DAC channel2 software trigger
Definition at line 4250 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) |
Definition at line 11568 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000) |
Definition at line 11569 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) |
Definition at line 11565 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) |
Definition at line 11566 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) |
Definition at line 11567 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP |
Definition at line 11571 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) |
Definition at line 11564 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) |
Definition at line 11562 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040) |
Definition at line 11559 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080) |
Definition at line 11560 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) |
Definition at line 11561 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) |
Definition at line 11553 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) |
Definition at line 11554 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) |
Definition at line 11555 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) |
Definition at line 11556 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) |
Definition at line 11557 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) |
Definition at line 11558 of file stm32f4xx.h.
| #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) |
Definition at line 11563 of file stm32f4xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000) |
Definition at line 11577 of file stm32f4xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB1_FZ_DBG_TIM10_STOP |
Definition at line 11577 of file stm32f4xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000) |
Definition at line 11578 of file stm32f4xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB1_FZ_DBG_TIM11_STOP |
Definition at line 11578 of file stm32f4xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) |
Definition at line 11574 of file stm32f4xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB1_FZ_DBG_TIM1_STOP |
Definition at line 11574 of file stm32f4xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) |
Definition at line 11575 of file stm32f4xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB1_FZ_DBG_TIM8_STOP |
Definition at line 11575 of file stm32f4xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000) |
Definition at line 11576 of file stm32f4xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB1_FZ_DBG_TIM9_STOP |
Definition at line 11576 of file stm32f4xx.h.
| #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
Definition at line 11543 of file stm32f4xx.h.
| #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
Definition at line 11545 of file stm32f4xx.h.
| #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
Definition at line 11544 of file stm32f4xx.h.
| #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
Definition at line 11546 of file stm32f4xx.h.
| #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
Definition at line 11548 of file stm32f4xx.h.
| #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040 |
Bit 0
Definition at line 11549 of file stm32f4xx.h.
| #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080 |
Bit 1
Definition at line 11550 of file stm32f4xx.h.
| #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
Definition at line 11539 of file stm32f4xx.h.
| #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
Definition at line 11540 of file stm32f4xx.h.
| #define DCMI_CR_CAPTURE ((uint32_t)0x00000001) |
Definition at line 4304 of file stm32f4xx.h.
Referenced by DCMI_CaptureCmd(), and DCMI_Init().
| #define DCMI_CR_CM ((uint32_t)0x00000002) |
Definition at line 4305 of file stm32f4xx.h.
Referenced by DCMI_Init().
| #define DCMI_CR_CRE ((uint32_t)0x00001000) |
Definition at line 4316 of file stm32f4xx.h.
| #define DCMI_CR_CROP ((uint32_t)0x00000004) |
Definition at line 4306 of file stm32f4xx.h.
Referenced by DCMI_CROPCmd().
| #define DCMI_CR_EDM_0 ((uint32_t)0x00000400) |
Definition at line 4314 of file stm32f4xx.h.
Referenced by DCMI_Init().
| #define DCMI_CR_EDM_1 ((uint32_t)0x00000800) |
Definition at line 4315 of file stm32f4xx.h.
Referenced by DCMI_Init().
| #define DCMI_CR_ENABLE ((uint32_t)0x00004000) |
Definition at line 4317 of file stm32f4xx.h.
Referenced by DCMI_Cmd(), and DCMI_Init().
| #define DCMI_CR_ESS ((uint32_t)0x00000010) |
Definition at line 4308 of file stm32f4xx.h.
Referenced by DCMI_Init().
| #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100) |
Definition at line 4312 of file stm32f4xx.h.
Referenced by DCMI_Init().
| #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200) |
Definition at line 4313 of file stm32f4xx.h.
Referenced by DCMI_Init().
| #define DCMI_CR_HSPOL ((uint32_t)0x00000040) |
Definition at line 4310 of file stm32f4xx.h.
Referenced by DCMI_Init().
| #define DCMI_CR_JPEG ((uint32_t)0x00000008) |
Definition at line 4307 of file stm32f4xx.h.
Referenced by DCMI_JPEGCmd().
| #define DCMI_CR_PCKPOL ((uint32_t)0x00000020) |
Definition at line 4309 of file stm32f4xx.h.
Referenced by DCMI_Init().
| #define DCMI_CR_VSPOL ((uint32_t)0x00000080) |
Definition at line 4311 of file stm32f4xx.h.
Referenced by DCMI_Init().
| #define DCMI_CWSIZE_CAPCNT ((uint32_t)0x00003FFF) |
Definition at line 4389 of file stm32f4xx.h.
| #define DCMI_CWSIZE_VLINE ((uint32_t)0x3FFF0000) |
Definition at line 4390 of file stm32f4xx.h.
| #define DCMI_CWSTRT_HOFFCNT ((uint32_t)0x00003FFF) |
Definition at line 4385 of file stm32f4xx.h.
| #define DCMI_CWSTRT_VST ((uint32_t)0x1FFF0000) |
Definition at line 4386 of file stm32f4xx.h.
| #define DCMI_DR_BYTE0 ((uint32_t)0x000000FF) |
Definition at line 4393 of file stm32f4xx.h.
| #define DCMI_DR_BYTE1 ((uint32_t)0x0000FF00) |
Definition at line 4394 of file stm32f4xx.h.
| #define DCMI_DR_BYTE2 ((uint32_t)0x00FF0000) |
Definition at line 4395 of file stm32f4xx.h.
| #define DCMI_DR_BYTE3 ((uint32_t)0xFF000000) |
Definition at line 4396 of file stm32f4xx.h.
| #define DCMI_ESCR_FEC ((uint32_t)0xFF000000) |
Definition at line 4376 of file stm32f4xx.h.
| #define DCMI_ESCR_FSC ((uint32_t)0x000000FF) |
Definition at line 4373 of file stm32f4xx.h.
| #define DCMI_ESCR_LEC ((uint32_t)0x00FF0000) |
Definition at line 4375 of file stm32f4xx.h.
| #define DCMI_ESCR_LSC ((uint32_t)0x0000FF00) |
Definition at line 4374 of file stm32f4xx.h.
| #define DCMI_ESUR_FEU ((uint32_t)0xFF000000) |
Definition at line 4382 of file stm32f4xx.h.
| #define DCMI_ESUR_FSU ((uint32_t)0x000000FF) |
Definition at line 4379 of file stm32f4xx.h.
| #define DCMI_ESUR_LEU ((uint32_t)0x00FF0000) |
Definition at line 4381 of file stm32f4xx.h.
| #define DCMI_ESUR_LSU ((uint32_t)0x0000FF00) |
Definition at line 4380 of file stm32f4xx.h.
| #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004) |
Definition at line 4365 of file stm32f4xx.h.
| #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001) |
Definition at line 4363 of file stm32f4xx.h.
| #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010) |
Definition at line 4367 of file stm32f4xx.h.
| #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC |
Definition at line 4370 of file stm32f4xx.h.
| #define DCMI_ICR_OVR_ISC ((uint32_t)0x00000002) |
Definition at line 4364 of file stm32f4xx.h.
| #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008) |
Definition at line 4366 of file stm32f4xx.h.
| #define DCMI_IER_ERR_IE ((uint32_t)0x00000004) |
Definition at line 4341 of file stm32f4xx.h.
| #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001) |
Definition at line 4339 of file stm32f4xx.h.
| #define DCMI_IER_LINE_IE ((uint32_t)0x00000010) |
Definition at line 4343 of file stm32f4xx.h.
| #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE |
Definition at line 4346 of file stm32f4xx.h.
| #define DCMI_IER_OVR_IE ((uint32_t)0x00000002) |
Definition at line 4340 of file stm32f4xx.h.
| #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008) |
Definition at line 4342 of file stm32f4xx.h.
| #define DCMI_MIS_ERR_MIS ((uint32_t)0x00000004) |
Definition at line 4351 of file stm32f4xx.h.
| #define DCMI_MIS_FRAME_MIS ((uint32_t)0x00000001) |
Definition at line 4349 of file stm32f4xx.h.
| #define DCMI_MIS_LINE_MIS ((uint32_t)0x00000010) |
Definition at line 4353 of file stm32f4xx.h.
| #define DCMI_MIS_OVR_MIS ((uint32_t)0x00000002) |
Definition at line 4350 of file stm32f4xx.h.
| #define DCMI_MIS_VSYNC_MIS ((uint32_t)0x00000008) |
Definition at line 4352 of file stm32f4xx.h.
| #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS |
Definition at line 4358 of file stm32f4xx.h.
| #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS |
Definition at line 4356 of file stm32f4xx.h.
| #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS |
Definition at line 4360 of file stm32f4xx.h.
| #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS |
Definition at line 4357 of file stm32f4xx.h.
| #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS |
Definition at line 4359 of file stm32f4xx.h.
| #define DCMI_RIS_ERR_RIS ((uint32_t)0x00000004) |
Definition at line 4327 of file stm32f4xx.h.
| #define DCMI_RIS_FRAME_RIS ((uint32_t)0x00000001) |
Definition at line 4325 of file stm32f4xx.h.
| #define DCMI_RIS_LINE_RIS ((uint32_t)0x00000010) |
Definition at line 4329 of file stm32f4xx.h.
| #define DCMI_RIS_OVR_RIS ((uint32_t)0x00000002) |
Definition at line 4326 of file stm32f4xx.h.
| #define DCMI_RIS_VSYNC_RIS ((uint32_t)0x00000008) |
Definition at line 4328 of file stm32f4xx.h.
| #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS |
Definition at line 4333 of file stm32f4xx.h.
| #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS |
Definition at line 4331 of file stm32f4xx.h.
| #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS |
Definition at line 4335 of file stm32f4xx.h.
| #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS |
Definition at line 4336 of file stm32f4xx.h.
| #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS |
Definition at line 4332 of file stm32f4xx.h.
| #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS |
Definition at line 4334 of file stm32f4xx.h.
| #define DCMI_SR_FNE ((uint32_t)0x00000004) |
Definition at line 4322 of file stm32f4xx.h.
| #define DCMI_SR_HSYNC ((uint32_t)0x00000001) |
Definition at line 4320 of file stm32f4xx.h.
| #define DCMI_SR_VSYNC ((uint32_t)0x00000002) |
Definition at line 4321 of file stm32f4xx.h.
| #define DFSDM_CHAWSCDR_AWFORD ((uint32_t)0x00C00000) |
AWFORD[1:0] Analog watchdog Sinc filter order on channel y
Definition at line 4432 of file stm32f4xx.h.
| #define DFSDM_CHAWSCDR_AWFORD_0 ((uint32_t)0x00400000) |
Analog watchdog Sinc filter order on channel y, Bit 0
Definition at line 4434 of file stm32f4xx.h.
| #define DFSDM_CHAWSCDR_AWFORD_1 ((uint32_t)0x00800000) |
Analog watchdog Sinc filter order on channel y, Bit 1
Definition at line 4433 of file stm32f4xx.h.
| #define DFSDM_CHAWSCDR_AWFOSR ((uint32_t)0x001F0000) |
AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y
Definition at line 4435 of file stm32f4xx.h.
| #define DFSDM_CHAWSCDR_BKSCD ((uint32_t)0x0000F000) |
BKSCD[3:0] Break signal assignment for short circuit detector on channel y
Definition at line 4436 of file stm32f4xx.h.
| #define DFSDM_CHAWSCDR_SCDT ((uint32_t)0x000000FF) |
SCDT[7:0] Short circuit detector threshold for channel y
Definition at line 4437 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_CHEN ((uint32_t)0x00000080) |
Channel y enable
Definition at line 4417 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_CHINSEL ((uint32_t)0x00000100) |
Serial inputs selection for channel y
Definition at line 4416 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_CKABEN ((uint32_t)0x00000040) |
Clock absence detector enable on channel y
Definition at line 4418 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_CKOUTDIV ((uint32_t)0x00FF0000) |
CKOUTDIV[7:0] output serial clock divider
Definition at line 4409 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_CKOUTSRC ((uint32_t)0x40000000) |
Output serial clock source selection
Definition at line 4408 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_DATMPX ((uint32_t)0x00003000) |
DATMPX[1:0] Input data multiplexer for channel y
Definition at line 4413 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_DATMPX_0 ((uint32_t)0x00001000) |
Input data multiplexer for channel y, Bit 0
Definition at line 4415 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_DATMPX_1 ((uint32_t)0x00002000) |
Input data multiplexer for channel y, Bit 1
Definition at line 4414 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_DATPACK ((uint32_t)0x0000C000) |
DATPACK[1:0] Data packing mode
Definition at line 4410 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_DATPACK_0 ((uint32_t)0x00004000) |
Data packing mode, Bit 0
Definition at line 4412 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_DATPACK_1 ((uint32_t)0x00008000) |
Data packing mode, Bit 1
Definition at line 4411 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_DFSDMEN ((uint32_t)0x80000000) |
Global enable for DFSDM interface
Definition at line 4407 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_SCDEN ((uint32_t)0x00000020) |
Short circuit detector enable on channel y
Definition at line 4419 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_SITP ((uint32_t)0x00000003) |
SITP[1:0] Serial interface type for channel y
Definition at line 4423 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_SITP_0 ((uint32_t)0x00000001) |
Serial interface type for channel y, Bit 0
Definition at line 4425 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_SITP_1 ((uint32_t)0x00000002) |
Serial interface type for channel y, Bit 1
Definition at line 4424 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_SPICKSEL ((uint32_t)0x0000000C) |
SPICKSEL[1:0] SPI clock select for channel y
Definition at line 4420 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_SPICKSEL_0 ((uint32_t)0x00000004) |
SPI clock select for channel y, Bit 0
Definition at line 4422 of file stm32f4xx.h.
| #define DFSDM_CHCFGR1_SPICKSEL_1 ((uint32_t)0x00000008) |
SPI clock select for channel y, Bit 1
Definition at line 4421 of file stm32f4xx.h.
| #define DFSDM_CHCFGR2_DTRBS ((uint32_t)0x000000F8) |
DTRBS[4:0] Data right bit-shift for channel y
Definition at line 4429 of file stm32f4xx.h.
| #define DFSDM_CHCFGR2_OFFSET ((uint32_t)0xFFFFFF00) |
OFFSET[23:0] 24-bit calibration offset for channel y
Definition at line 4428 of file stm32f4xx.h.
| #define DFSDM_CHDATINR_INDAT0 ((uint32_t)0x0000FFFF) |
INDAT0[31:16] Input data for channel y or channel (y+1)
Definition at line 4443 of file stm32f4xx.h.
| #define DFSDM_CHDATINR_INDAT1 ((uint32_t)0xFFFF0000) |
INDAT0[15:0] Input data for channel y
Definition at line 4444 of file stm32f4xx.h.
| #define DFSDM_CHWDATR_WDATA ((uint32_t)0x0000FFFF) |
WDATA[15:0] Input channel y watchdog data
Definition at line 4440 of file stm32f4xx.h.
| #define DFSDM_FLTAWCFR_CLRAWHTF ((uint32_t)0x00000F00) |
CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag
Definition at line 4530 of file stm32f4xx.h.
| #define DFSDM_FLTAWCFR_CLRAWLTF ((uint32_t)0x0000000F) |
CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag
Definition at line 4531 of file stm32f4xx.h.
| #define DFSDM_FLTAWHTR_AWHT ((uint32_t)0xFFFFFF00) |
AWHT[23:0] Analog watchdog high threshold
Definition at line 4518 of file stm32f4xx.h.
| #define DFSDM_FLTAWHTR_BKAWH ((uint32_t)0x0000000F) |
BKAWH[3:0] Break signal assignment to analog watchdog high threshold event
Definition at line 4519 of file stm32f4xx.h.
| #define DFSDM_FLTAWLTR_AWLT ((uint32_t)0xFFFFFF00) |
AWLT[23:0] Analog watchdog low threshold
Definition at line 4522 of file stm32f4xx.h.
| #define DFSDM_FLTAWLTR_BKAWL ((uint32_t)0x0000000F) |
BKAWL[3:0] Break signal assignment to analog watchdog low threshold event
Definition at line 4523 of file stm32f4xx.h.
| #define DFSDM_FLTAWSR_AWHTF ((uint32_t)0x00000F00) |
AWHTF[15:8] Analog watchdog high threshold error on given channels
Definition at line 4526 of file stm32f4xx.h.
| #define DFSDM_FLTAWSR_AWLTF ((uint32_t)0x0000000F) |
AWLTF[7:0] Analog watchdog low threshold error on given channels
Definition at line 4527 of file stm32f4xx.h.
| #define DFSDM_FLTCNVTIMR_CNVCNT ((uint32_t)0xFFFFFFF0) |
CNVCNT[27:0]: 28-bit timer counting conversion time
Definition at line 4542 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_AWFSEL ((uint32_t)0x40000000) |
Analog watchdog fast mode select
Definition at line 4449 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_DFEN ((uint32_t)0x00000001) |
DFSDM enable
Definition at line 4467 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_FAST ((uint32_t)0x20000000) |
Fast conversion mode selection
Definition at line 4450 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_JDMAEN ((uint32_t)0x00000020) |
DMA channel enabled to read data for the injected channel group
Definition at line 4463 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_JEXTEN ((uint32_t)0x00006000) |
JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions
Definition at line 4456 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_JEXTEN_0 ((uint32_t)0x00002000) |
Trigger enable and trigger edge selection for injected conversions, Bit 0
Definition at line 4458 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_JEXTEN_1 ((uint32_t)0x00004000) |
Trigger enable and trigger edge selection for injected conversions, Bit 1
Definition at line 4457 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_JEXTSEL ((uint32_t)0x00000700) |
JEXTSEL[2:0]Trigger signal selection for launching injected conversions
Definition at line 4459 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_JEXTSEL_0 ((uint32_t)0x00000100) |
Trigger signal selection for launching injected conversions, Bit 0
Definition at line 4462 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_JEXTSEL_1 ((uint32_t)0x00000200) |
Trigger signal selection for launching injected conversions, Bit 1
Definition at line 4461 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_JEXTSEL_2 ((uint32_t)0x00000400) |
Trigger signal selection for launching injected conversions, Bit 2
Definition at line 4460 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_JSCAN ((uint32_t)0x00000010) |
Scanning conversion in continuous mode selection for injected conversions
Definition at line 4464 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_JSWSTART ((uint32_t)0x00000002) |
Start the conversion of the injected group of channels
Definition at line 4466 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_JSYNC ((uint32_t)0x00000008) |
Launch an injected conversion synchronously with DFSDMx JSWSTART trigger
Definition at line 4465 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_RCH ((uint32_t)0x07000000) |
RCH[2:0] Regular channel selection
Definition at line 4451 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_RCONT ((uint32_t)0x00040000) |
Continuous mode selection for regular conversions
Definition at line 4454 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_RDMAEN ((uint32_t)0x00200000) |
DMA channel enabled to read data for the regular conversion
Definition at line 4452 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_RSWSTART ((uint32_t)0x00020000) |
Software start of a conversion on the regular channel
Definition at line 4455 of file stm32f4xx.h.
| #define DFSDM_FLTCR1_RSYNC ((uint32_t)0x00080000) |
Launch regular conversion synchronously with DFSDMx
Definition at line 4453 of file stm32f4xx.h.
| #define DFSDM_FLTCR2_AWDCH ((uint32_t)0x000F0000) |
AWDCH[7:0] Analog watchdog channel selection
Definition at line 4470 of file stm32f4xx.h.
| #define DFSDM_FLTCR2_AWDIE ((uint32_t)0x00000010) |
Analog watchdog interrupt enable
Definition at line 4474 of file stm32f4xx.h.
| #define DFSDM_FLTCR2_CKABIE ((uint32_t)0x00000040) |
Clock absence interrupt enable
Definition at line 4472 of file stm32f4xx.h.
| #define DFSDM_FLTCR2_EXCH ((uint32_t)0x00000F00) |
EXCH[7:0] Extreme detector channel selection
Definition at line 4471 of file stm32f4xx.h.
| #define DFSDM_FLTCR2_JEOCIE ((uint32_t)0x00000001) |
Injected end of conversion interrupt enable
Definition at line 4478 of file stm32f4xx.h.
| #define DFSDM_FLTCR2_JOVRIE ((uint32_t)0x00000004) |
Injected data overrun interrupt enable
Definition at line 4476 of file stm32f4xx.h.
| #define DFSDM_FLTCR2_REOCIE ((uint32_t)0x00000002) |
Regular end of conversion interrupt enable
Definition at line 4477 of file stm32f4xx.h.
| #define DFSDM_FLTCR2_ROVRIE ((uint32_t)0x00000008) |
Regular data overrun interrupt enable
Definition at line 4475 of file stm32f4xx.h.
| #define DFSDM_FLTCR2_SCDIE ((uint32_t)0x00000020) |
Short circuit detector interrupt enable
Definition at line 4473 of file stm32f4xx.h.
| #define DFSDM_FLTEXMAX_EXMAX ((uint32_t)0xFFFFFF00) |
EXMAX[23:0] Extreme detector maximum value
Definition at line 4534 of file stm32f4xx.h.
| #define DFSDM_FLTEXMAX_EXMAXCH ((uint32_t)0x00000007) |
EXMAXCH[2:0] Extreme detector maximum data channel
Definition at line 4535 of file stm32f4xx.h.
| #define DFSDM_FLTEXMIN_EXMIN ((uint32_t)0xFFFFFF00) |
EXMIN[23:0] Extreme detector minimum value
Definition at line 4538 of file stm32f4xx.h.
| #define DFSDM_FLTEXMIN_EXMINCH ((uint32_t)0x00000007) |
EXMINCH[2:0] Extreme detector minimum data channel
Definition at line 4539 of file stm32f4xx.h.
| #define DFSDM_FLTFCR_FORD ((uint32_t)0xE0000000) |
FORD[2:0] Sinc filter order
Definition at line 4501 of file stm32f4xx.h.
| #define DFSDM_FLTFCR_FORD_0 ((uint32_t)0x20000000) |
Sinc filter order, Bit 0
Definition at line 4504 of file stm32f4xx.h.
| #define DFSDM_FLTFCR_FORD_1 ((uint32_t)0x40000000) |
Sinc filter order, Bit 1
Definition at line 4503 of file stm32f4xx.h.
| #define DFSDM_FLTFCR_FORD_2 ((uint32_t)0x80000000) |
Sinc filter order, Bit 2
Definition at line 4502 of file stm32f4xx.h.
| #define DFSDM_FLTFCR_FOSR ((uint32_t)0x03FF0000) |
FOSR[9:0] Sinc filter oversampling ratio (decimation rate)
Definition at line 4505 of file stm32f4xx.h.
| #define DFSDM_FLTFCR_IOSR ((uint32_t)0x000000FF) |
IOSR[7:0] Integrator oversampling ratio (averaging length)
Definition at line 4506 of file stm32f4xx.h.
| #define DFSDM_FLTICR_CLRCKABF ((uint32_t)0x000F0000) |
CLRCKABF[7:0] Clear the clock absence flag
Definition at line 4493 of file stm32f4xx.h.
| #define DFSDM_FLTICR_CLRJOVRF ((uint32_t)0x00000004) |
Clear the injected conversion overrun flag
Definition at line 4495 of file stm32f4xx.h.
| #define DFSDM_FLTICR_CLRROVRF ((uint32_t)0x00000008) |
Clear the regular conversion overrun flag
Definition at line 4494 of file stm32f4xx.h.
| #define DFSDM_FLTICR_CLRSCSDF ((uint32_t)0x0F000000) |
CLRSCSDF[7:0] Clear the short circuit detector flag
Definition at line 4492 of file stm32f4xx.h.
| #define DFSDM_FLTISR_AWDF ((uint32_t)0x00000010) |
Analog watchdog
Definition at line 4485 of file stm32f4xx.h.
| #define DFSDM_FLTISR_CKABF ((uint32_t)0x000F0000) |
CKABF[7:0] Clock absence flag
Definition at line 4482 of file stm32f4xx.h.
| #define DFSDM_FLTISR_JCIP ((uint32_t)0x00002000) |
Injected conversion in progress status
Definition at line 4484 of file stm32f4xx.h.
| #define DFSDM_FLTISR_JEOCF ((uint32_t)0x00000001) |
End of injected conversion flag
Definition at line 4489 of file stm32f4xx.h.
| #define DFSDM_FLTISR_JOVRF ((uint32_t)0x00000004) |
Injected conversion overrun flag
Definition at line 4487 of file stm32f4xx.h.
| #define DFSDM_FLTISR_RCIP ((uint32_t)0x00004000) |
Regular conversion in progress status
Definition at line 4483 of file stm32f4xx.h.
| #define DFSDM_FLTISR_REOCF ((uint32_t)0x00000002) |
End of regular conversion flag
Definition at line 4488 of file stm32f4xx.h.
| #define DFSDM_FLTISR_ROVRF ((uint32_t)0x00000008) |
Regular conversion overrun flag
Definition at line 4486 of file stm32f4xx.h.
| #define DFSDM_FLTISR_SCDF ((uint32_t)0x0F000000) |
SCDF[7:0] Short circuit detector flag
Definition at line 4481 of file stm32f4xx.h.
| #define DFSDM_FLTJCHGR_JCHG ((uint32_t)0x000000FF) |
JCHG[7:0] Injected channel group selection
Definition at line 4498 of file stm32f4xx.h.
| #define DFSDM_FLTJDATAR_JDATA ((uint32_t)0xFFFFFF00) |
JDATA[23:0] Injected group conversion data
Definition at line 4509 of file stm32f4xx.h.
| #define DFSDM_FLTJDATAR_JDATACH ((uint32_t)0x00000007) |
JDATACH[2:0] Injected channel most recently converted
Definition at line 4510 of file stm32f4xx.h.
| #define DFSDM_FLTRDATAR_RDATA ((uint32_t)0xFFFFFF00) |
RDATA[23:0] Regular channel conversion data
Definition at line 4513 of file stm32f4xx.h.
| #define DFSDM_FLTRDATAR_RDATACH ((uint32_t)0x00000007) |
RDATACH[2:0] Regular channel most recently converted
Definition at line 4515 of file stm32f4xx.h.
| #define DFSDM_FLTRDATAR_RPEND ((uint32_t)0x00000010) |
RPEND Regular channel pending data
Definition at line 4514 of file stm32f4xx.h.
| #define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) |
Dead Time
Definition at line 4868 of file stm32f4xx.h.
| #define DMA2D_AMTCR_EN ((uint32_t)0x00000001) |
| #define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) |
Memory Address
Definition at line 4813 of file stm32f4xx.h.
| #define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) |
| #define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) |
| #define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) |
| #define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) |
Memory Address
Definition at line 4759 of file stm32f4xx.h.
| #define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) |
| #define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) |
Alpha value
Definition at line 4799 of file stm32f4xx.h.
| #define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) |
Alpha mode AM[1:0]
Definition at line 4796 of file stm32f4xx.h.
| #define DMA2D_BGPFCCR_AM_0 ((uint32_t)0x00010000) |
Alpha mode AM bit 0
Definition at line 4797 of file stm32f4xx.h.
| #define DMA2D_BGPFCCR_AM_1 ((uint32_t)0x00020000) |
Alpha mode AM bit 1
Definition at line 4798 of file stm32f4xx.h.
| #define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) |
CLUT Color mode
Definition at line 4793 of file stm32f4xx.h.
| #define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) |
Input color mode CM[3:0]
Definition at line 4788 of file stm32f4xx.h.
| #define DMA2D_BGPFCCR_CM_0 ((uint32_t)0x00000001) |
Input color mode CM bit 0
Definition at line 4789 of file stm32f4xx.h.
| #define DMA2D_BGPFCCR_CM_1 ((uint32_t)0x00000002) |
Input color mode CM bit 1
Definition at line 4790 of file stm32f4xx.h.
| #define DMA2D_BGPFCCR_CM_2 ((uint32_t)0x00000004) |
Input color mode CM bit 2
Definition at line 4791 of file stm32f4xx.h.
| #define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) |
CLUT size
Definition at line 4795 of file stm32f4xx.h.
| #define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) |
| #define DMA2D_CR_ABORT ((uint32_t)0x00000004) |
| #define DMA2D_CR_CAEIE ((uint32_t)0x00000800) |
CLUT Access Error Interrupt Enable
Definition at line 4718 of file stm32f4xx.h.
| #define DMA2D_CR_CEIE ((uint32_t)0x00002000) |
Configuration Error Interrupt Enable
Definition at line 4720 of file stm32f4xx.h.
| #define DMA2D_CR_CTCIE ((uint32_t)0x00001000) |
CLUT Transfer Complete Interrupt Enable
Definition at line 4719 of file stm32f4xx.h.
| #define DMA2D_CR_MODE ((uint32_t)0x00030000) |
DMA2D Mode
Definition at line 4721 of file stm32f4xx.h.
| #define DMA2D_CR_START ((uint32_t)0x00000001) |
| #define DMA2D_CR_SUSP ((uint32_t)0x00000002) |
| #define DMA2D_CR_TCIE ((uint32_t)0x00000200) |
Transfer Complete Interrupt Enable
Definition at line 4716 of file stm32f4xx.h.
| #define DMA2D_CR_TEIE ((uint32_t)0x00000100) |
Transfer Error Interrupt Enable
Definition at line 4715 of file stm32f4xx.h.
| #define DMA2D_CR_TWIE ((uint32_t)0x00000400) |
Transfer Watermark Interrupt Enable
Definition at line 4717 of file stm32f4xx.h.
| #define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) |
Memory Address
Definition at line 4809 of file stm32f4xx.h.
| #define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) |
| #define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) |
| #define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) |
| #define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) |
Memory Address
Definition at line 4751 of file stm32f4xx.h.
| #define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) |
| #define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) |
Alpha value
Definition at line 4778 of file stm32f4xx.h.
| #define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) |
Alpha mode AM[1:0]
Definition at line 4775 of file stm32f4xx.h.
| #define DMA2D_FGPFCCR_AM_0 ((uint32_t)0x00010000) |
Alpha mode AM bit 0
Definition at line 4776 of file stm32f4xx.h.
| #define DMA2D_FGPFCCR_AM_1 ((uint32_t)0x00020000) |
Alpha mode AM bit 1
Definition at line 4777 of file stm32f4xx.h.
| #define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) |
CLUT Color mode
Definition at line 4772 of file stm32f4xx.h.
| #define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) |
Input color mode CM[3:0]
Definition at line 4767 of file stm32f4xx.h.
| #define DMA2D_FGPFCCR_CM_0 ((uint32_t)0x00000001) |
Input color mode CM bit 0
Definition at line 4768 of file stm32f4xx.h.
| #define DMA2D_FGPFCCR_CM_1 ((uint32_t)0x00000002) |
Input color mode CM bit 1
Definition at line 4769 of file stm32f4xx.h.
| #define DMA2D_FGPFCCR_CM_2 ((uint32_t)0x00000004) |
Input color mode CM bit 2
Definition at line 4770 of file stm32f4xx.h.
| #define DMA2D_FGPFCCR_CM_3 ((uint32_t)0x00000008) |
Input color mode CM bit 3
Definition at line 4771 of file stm32f4xx.h.
| #define DMA2D_FGPFCCR_CM_3 ((uint32_t)0x00000008) |
Input color mode CM bit 3
Definition at line 4771 of file stm32f4xx.h.
| #define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) |
CLUT size
Definition at line 4774 of file stm32f4xx.h.
| #define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) |
| #define DMA2D_IFCR_CAECIF ((uint32_t)0x00000008) |
Clears CLUT Access Error Interrupt Flag
Definition at line 4737 of file stm32f4xx.h.
| #define DMA2D_IFCR_CCEIF ((uint32_t)0x00000020) |
Clears Configuration Error Interrupt Flag
Definition at line 4739 of file stm32f4xx.h.
| #define DMA2D_IFCR_CCTCIF ((uint32_t)0x00000010) |
Clears CLUT Transfer Complete Interrupt Flag
Definition at line 4738 of file stm32f4xx.h.
| #define DMA2D_IFCR_CTCIF ((uint32_t)0x00000002) |
Clears Transfer Complete Interrupt Flag
Definition at line 4735 of file stm32f4xx.h.
| #define DMA2D_IFCR_CTEIF ((uint32_t)0x00000001) |
Clears Transfer Error Interrupt Flag
Definition at line 4734 of file stm32f4xx.h.
| #define DMA2D_IFCR_CTWIF ((uint32_t)0x00000004) |
Clears Transfer Watermark Interrupt Flag
Definition at line 4736 of file stm32f4xx.h.
| #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF |
Clears CLUT Access Error Interrupt Flag
Definition at line 4745 of file stm32f4xx.h.
| #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF |
Clears Configuration Error Interrupt Flag
Definition at line 4747 of file stm32f4xx.h.
| #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF |
Clears CLUT Transfer Complete Interrupt Flag
Definition at line 4746 of file stm32f4xx.h.
| #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF |
Clears Transfer Complete Interrupt Flag
Definition at line 4743 of file stm32f4xx.h.
| #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF |
Clears Transfer Error Interrupt Flag
Definition at line 4742 of file stm32f4xx.h.
| #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF |
Clears Transfer Watermark Interrupt Flag
Definition at line 4744 of file stm32f4xx.h.
| #define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) |
CLUT Access Error Interrupt Flag
Definition at line 4728 of file stm32f4xx.h.
| #define DMA2D_ISR_CEIF ((uint32_t)0x00000020) |
Configuration Error Interrupt Flag
Definition at line 4730 of file stm32f4xx.h.
| #define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) |
CLUT Transfer Complete Interrupt Flag
Definition at line 4729 of file stm32f4xx.h.
| #define DMA2D_ISR_TCIF ((uint32_t)0x00000002) |
Transfer Complete Interrupt Flag
Definition at line 4726 of file stm32f4xx.h.
| #define DMA2D_ISR_TEIF ((uint32_t)0x00000001) |
Transfer Error Interrupt Flag
Definition at line 4725 of file stm32f4xx.h.
| #define DMA2D_ISR_TWIF ((uint32_t)0x00000004) |
Transfer Watermark Interrupt Flag
Definition at line 4727 of file stm32f4xx.h.
| #define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) |
Line Watermark
Definition at line 4863 of file stm32f4xx.h.
| #define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) |
| #define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) |
| #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) |
Alpha Channel Value Mode_RGB565
Definition at line 4829 of file stm32f4xx.h.
| #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) |
Alpha Channel Value Mode_ARGB4444
Definition at line 4840 of file stm32f4xx.h.
| #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) |
Alpha Channel Value
Definition at line 4846 of file stm32f4xx.h.
| #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) |
<Mode_ARGB8888/RGB888 BLUE Value
Definition at line 4826 of file stm32f4xx.h.
| #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) |
BLUE Value
Definition at line 4832 of file stm32f4xx.h.
| #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) |
BLUE Value
Definition at line 4837 of file stm32f4xx.h.
| #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) |
BLUE Value
Definition at line 4843 of file stm32f4xx.h.
| #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) |
GREEN Value
Definition at line 4827 of file stm32f4xx.h.
| #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) |
GREEN Value
Definition at line 4833 of file stm32f4xx.h.
| #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) |
GREEN Value
Definition at line 4838 of file stm32f4xx.h.
| #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) |
GREEN Value
Definition at line 4844 of file stm32f4xx.h.
| #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) |
Red Value
Definition at line 4828 of file stm32f4xx.h.
| #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) |
Red Value Mode_ARGB1555
Definition at line 4834 of file stm32f4xx.h.
| #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) |
Red Value
Definition at line 4839 of file stm32f4xx.h.
| #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) |
Red Value
Definition at line 4845 of file stm32f4xx.h.
| #define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) |
Memory Address
Definition at line 4850 of file stm32f4xx.h.
| #define DMA2D_OOR_LO ((uint32_t)0x00003FFF) |
| #define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) |
| #define DMA2D_OPFCCR_CM_0 ((uint32_t)0x00000001) |
Color mode CM bit 0
Definition at line 4818 of file stm32f4xx.h.
| #define DMA2D_OPFCCR_CM_1 ((uint32_t)0x00000002) |
Color mode CM bit 1
Definition at line 4819 of file stm32f4xx.h.
| #define DMA2D_OPFCCR_CM_2 ((uint32_t)0x00000004) |
Color mode CM bit 2
Definition at line 4820 of file stm32f4xx.h.
| #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004) |
Definition at line 4701 of file stm32f4xx.h.
| #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100) |
Definition at line 4696 of file stm32f4xx.h.
| #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000) |
Definition at line 4691 of file stm32f4xx.h.
| #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000) |
Definition at line 4686 of file stm32f4xx.h.
| #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001) |
Definition at line 4702 of file stm32f4xx.h.
| #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040) |
Definition at line 4697 of file stm32f4xx.h.
| #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000) |
Definition at line 4692 of file stm32f4xx.h.
| #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000) |
Definition at line 4687 of file stm32f4xx.h.
| #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010) |
Definition at line 4699 of file stm32f4xx.h.
| #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400) |
Definition at line 4694 of file stm32f4xx.h.
| #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000) |
Definition at line 4689 of file stm32f4xx.h.
| #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000) |
Definition at line 4684 of file stm32f4xx.h.
| #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020) |
Definition at line 4698 of file stm32f4xx.h.
| #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800) |
Definition at line 4693 of file stm32f4xx.h.
| #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000) |
Definition at line 4688 of file stm32f4xx.h.
| #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000) |
Definition at line 4683 of file stm32f4xx.h.
| #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008) |
Definition at line 4700 of file stm32f4xx.h.
| #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200) |
Definition at line 4695 of file stm32f4xx.h.
| #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000) |
Definition at line 4690 of file stm32f4xx.h.
| #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000) |
Definition at line 4685 of file stm32f4xx.h.
| #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004) |
Definition at line 4657 of file stm32f4xx.h.
| #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100) |
Definition at line 4652 of file stm32f4xx.h.
| #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000) |
Definition at line 4647 of file stm32f4xx.h.
| #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000) |
Definition at line 4642 of file stm32f4xx.h.
| #define DMA_HISR_FEIF4 ((uint32_t)0x00000001) |
Definition at line 4658 of file stm32f4xx.h.
| #define DMA_HISR_FEIF5 ((uint32_t)0x00000040) |
Definition at line 4653 of file stm32f4xx.h.
| #define DMA_HISR_FEIF6 ((uint32_t)0x00010000) |
Definition at line 4648 of file stm32f4xx.h.
| #define DMA_HISR_FEIF7 ((uint32_t)0x00400000) |
Definition at line 4643 of file stm32f4xx.h.
| #define DMA_HISR_HTIF4 ((uint32_t)0x00000010) |
Definition at line 4655 of file stm32f4xx.h.
| #define DMA_HISR_HTIF5 ((uint32_t)0x00000400) |
Definition at line 4650 of file stm32f4xx.h.
| #define DMA_HISR_HTIF6 ((uint32_t)0x00100000) |
Definition at line 4645 of file stm32f4xx.h.
| #define DMA_HISR_HTIF7 ((uint32_t)0x04000000) |
Definition at line 4640 of file stm32f4xx.h.
| #define DMA_HISR_TCIF4 ((uint32_t)0x00000020) |
Definition at line 4654 of file stm32f4xx.h.
| #define DMA_HISR_TCIF5 ((uint32_t)0x00000800) |
Definition at line 4649 of file stm32f4xx.h.
| #define DMA_HISR_TCIF6 ((uint32_t)0x00200000) |
Definition at line 4644 of file stm32f4xx.h.
| #define DMA_HISR_TCIF7 ((uint32_t)0x08000000) |
Definition at line 4639 of file stm32f4xx.h.
| #define DMA_HISR_TEIF4 ((uint32_t)0x00000008) |
Definition at line 4656 of file stm32f4xx.h.
| #define DMA_HISR_TEIF5 ((uint32_t)0x00000200) |
Definition at line 4651 of file stm32f4xx.h.
| #define DMA_HISR_TEIF6 ((uint32_t)0x00080000) |
Definition at line 4646 of file stm32f4xx.h.
| #define DMA_HISR_TEIF7 ((uint32_t)0x02000000) |
Definition at line 4641 of file stm32f4xx.h.
| #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004) |
Definition at line 4679 of file stm32f4xx.h.
| #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100) |
Definition at line 4674 of file stm32f4xx.h.
| #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000) |
Definition at line 4669 of file stm32f4xx.h.
| #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000) |
Definition at line 4664 of file stm32f4xx.h.
| #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001) |
Definition at line 4680 of file stm32f4xx.h.
| #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040) |
Definition at line 4675 of file stm32f4xx.h.
| #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000) |
Definition at line 4670 of file stm32f4xx.h.
| #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000) |
Definition at line 4665 of file stm32f4xx.h.
| #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010) |
Definition at line 4677 of file stm32f4xx.h.
| #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400) |
Definition at line 4672 of file stm32f4xx.h.
| #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000) |
Definition at line 4667 of file stm32f4xx.h.
| #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000) |
Definition at line 4662 of file stm32f4xx.h.
| #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020) |
Definition at line 4676 of file stm32f4xx.h.
| #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800) |
Definition at line 4671 of file stm32f4xx.h.
| #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000) |
Definition at line 4666 of file stm32f4xx.h.
| #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000) |
Definition at line 4661 of file stm32f4xx.h.
| #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008) |
Definition at line 4678 of file stm32f4xx.h.
| #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200) |
Definition at line 4673 of file stm32f4xx.h.
| #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000) |
Definition at line 4668 of file stm32f4xx.h.
| #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000) |
Definition at line 4663 of file stm32f4xx.h.
| #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004) |
Definition at line 4635 of file stm32f4xx.h.
| #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100) |
Definition at line 4630 of file stm32f4xx.h.
| #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000) |
Definition at line 4625 of file stm32f4xx.h.
| #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000) |
Definition at line 4620 of file stm32f4xx.h.
| #define DMA_LISR_FEIF0 ((uint32_t)0x00000001) |
Definition at line 4636 of file stm32f4xx.h.
| #define DMA_LISR_FEIF1 ((uint32_t)0x00000040) |
Definition at line 4631 of file stm32f4xx.h.
| #define DMA_LISR_FEIF2 ((uint32_t)0x00010000) |
Definition at line 4626 of file stm32f4xx.h.
| #define DMA_LISR_FEIF3 ((uint32_t)0x00400000) |
Definition at line 4621 of file stm32f4xx.h.
| #define DMA_LISR_HTIF0 ((uint32_t)0x00000010) |
Definition at line 4633 of file stm32f4xx.h.
| #define DMA_LISR_HTIF1 ((uint32_t)0x00000400) |
Definition at line 4628 of file stm32f4xx.h.
| #define DMA_LISR_HTIF2 ((uint32_t)0x00100000) |
Definition at line 4623 of file stm32f4xx.h.
| #define DMA_LISR_HTIF3 ((uint32_t)0x04000000) |
Definition at line 4618 of file stm32f4xx.h.
| #define DMA_LISR_TCIF0 ((uint32_t)0x00000020) |
Definition at line 4632 of file stm32f4xx.h.
| #define DMA_LISR_TCIF1 ((uint32_t)0x00000800) |
Definition at line 4627 of file stm32f4xx.h.
| #define DMA_LISR_TCIF2 ((uint32_t)0x00200000) |
Definition at line 4622 of file stm32f4xx.h.
| #define DMA_LISR_TCIF3 ((uint32_t)0x08000000) |
Definition at line 4617 of file stm32f4xx.h.
| #define DMA_LISR_TEIF0 ((uint32_t)0x00000008) |
Definition at line 4634 of file stm32f4xx.h.
| #define DMA_LISR_TEIF1 ((uint32_t)0x00000200) |
Definition at line 4629 of file stm32f4xx.h.
| #define DMA_LISR_TEIF2 ((uint32_t)0x00080000) |
Definition at line 4624 of file stm32f4xx.h.
| #define DMA_LISR_TEIF3 ((uint32_t)0x02000000) |
Definition at line 4619 of file stm32f4xx.h.
| #define DMA_SxCR_ACK ((uint32_t)0x00100000) |
Definition at line 4560 of file stm32f4xx.h.
| #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000) |
Definition at line 4550 of file stm32f4xx.h.
Referenced by DMA_Init().
| #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000) |
Definition at line 4551 of file stm32f4xx.h.
| #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000) |
Definition at line 4552 of file stm32f4xx.h.
| #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) |
Definition at line 4553 of file stm32f4xx.h.
| #define DMA_SxCR_CIRC ((uint32_t)0x00000100) |
Definition at line 4575 of file stm32f4xx.h.
Referenced by DMA_Init().
| #define DMA_SxCR_CT ((uint32_t)0x00080000) |
Definition at line 4561 of file stm32f4xx.h.
Referenced by DMA_DoubleBufferModeConfig(), and DMA_GetCurrentMemoryTarget().
| #define DMA_SxCR_DBM ((uint32_t)0x00040000) |
Definition at line 4562 of file stm32f4xx.h.
Referenced by DMA_DoubleBufferModeCmd().
| #define DMA_SxCR_DIR ((uint32_t)0x000000C0) |
Definition at line 4576 of file stm32f4xx.h.
Referenced by DMA_Init().
| #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040) |
Definition at line 4577 of file stm32f4xx.h.
| #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080) |
Definition at line 4578 of file stm32f4xx.h.
| #define DMA_SxCR_DMEIE ((uint32_t)0x00000002) |
Definition at line 4583 of file stm32f4xx.h.
| #define DMA_SxCR_EN ((uint32_t)0x00000001) |
Definition at line 4584 of file stm32f4xx.h.
Referenced by DMA_Cmd(), DMA_DeInit(), and DMA_GetCmdStatus().
| #define DMA_SxCR_HTIE ((uint32_t)0x00000008) |
Definition at line 4581 of file stm32f4xx.h.
| #define DMA_SxCR_MBURST ((uint32_t)0x01800000) |
Definition at line 4554 of file stm32f4xx.h.
Referenced by DMA_Init().
| #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000) |
Definition at line 4555 of file stm32f4xx.h.
| #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000) |
Definition at line 4556 of file stm32f4xx.h.
| #define DMA_SxCR_MINC ((uint32_t)0x00000400) |
Definition at line 4573 of file stm32f4xx.h.
Referenced by DMA_Init().
| #define DMA_SxCR_MSIZE ((uint32_t)0x00006000) |
Definition at line 4567 of file stm32f4xx.h.
Referenced by DMA_Init().
| #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000) |
Definition at line 4568 of file stm32f4xx.h.
| #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000) |
Definition at line 4569 of file stm32f4xx.h.
| #define DMA_SxCR_PBURST ((uint32_t)0x00600000) |
Definition at line 4557 of file stm32f4xx.h.
Referenced by DMA_Init().
| #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000) |
Definition at line 4558 of file stm32f4xx.h.
| #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000) |
Definition at line 4559 of file stm32f4xx.h.
| #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020) |
Definition at line 4579 of file stm32f4xx.h.
Referenced by DMA_FlowControllerConfig().
| #define DMA_SxCR_PINC ((uint32_t)0x00000200) |
Definition at line 4574 of file stm32f4xx.h.
Referenced by DMA_Init().
| #define DMA_SxCR_PINCOS ((uint32_t)0x00008000) |
Definition at line 4566 of file stm32f4xx.h.
Referenced by DMA_PeriphIncOffsetSizeConfig().
| #define DMA_SxCR_PL ((uint32_t)0x00030000) |
Definition at line 4563 of file stm32f4xx.h.
Referenced by DMA_Init().
| #define DMA_SxCR_PL_0 ((uint32_t)0x00010000) |
Definition at line 4564 of file stm32f4xx.h.
| #define DMA_SxCR_PL_1 ((uint32_t)0x00020000) |
Definition at line 4565 of file stm32f4xx.h.
| #define DMA_SxCR_PSIZE ((uint32_t)0x00001800) |
Definition at line 4570 of file stm32f4xx.h.
Referenced by DMA_Init().
| #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800) |
Definition at line 4571 of file stm32f4xx.h.
| #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000) |
Definition at line 4572 of file stm32f4xx.h.
| #define DMA_SxCR_TCIE ((uint32_t)0x00000010) |
Definition at line 4580 of file stm32f4xx.h.
| #define DMA_SxCR_TEIE ((uint32_t)0x00000004) |
Definition at line 4582 of file stm32f4xx.h.
| #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004) |
Definition at line 4611 of file stm32f4xx.h.
Referenced by DMA_Init().
| #define DMA_SxFCR_FEIE ((uint32_t)0x00000080) |
Definition at line 4606 of file stm32f4xx.h.
| #define DMA_SxFCR_FS ((uint32_t)0x00000038) |
Definition at line 4607 of file stm32f4xx.h.
Referenced by DMA_GetFIFOStatus().
| #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008) |
Definition at line 4608 of file stm32f4xx.h.
| #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010) |
Definition at line 4609 of file stm32f4xx.h.
| #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020) |
Definition at line 4610 of file stm32f4xx.h.
| #define DMA_SxFCR_FTH ((uint32_t)0x00000003) |
Definition at line 4612 of file stm32f4xx.h.
Referenced by DMA_Init().
| #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001) |
Definition at line 4613 of file stm32f4xx.h.
| #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002) |
Definition at line 4614 of file stm32f4xx.h.
| #define DMA_SxNDT ((uint32_t)0x0000FFFF) |
Definition at line 4587 of file stm32f4xx.h.
| #define DMA_SxNDT_0 ((uint32_t)0x00000001) |
Definition at line 4588 of file stm32f4xx.h.
| #define DMA_SxNDT_1 ((uint32_t)0x00000002) |
Definition at line 4589 of file stm32f4xx.h.
| #define DMA_SxNDT_10 ((uint32_t)0x00000400) |
Definition at line 4598 of file stm32f4xx.h.
| #define DMA_SxNDT_11 ((uint32_t)0x00000800) |
Definition at line 4599 of file stm32f4xx.h.
| #define DMA_SxNDT_12 ((uint32_t)0x00001000) |
Definition at line 4600 of file stm32f4xx.h.
| #define DMA_SxNDT_13 ((uint32_t)0x00002000) |
Definition at line 4601 of file stm32f4xx.h.
| #define DMA_SxNDT_14 ((uint32_t)0x00004000) |
Definition at line 4602 of file stm32f4xx.h.
| #define DMA_SxNDT_15 ((uint32_t)0x00008000) |
Definition at line 4603 of file stm32f4xx.h.
| #define DMA_SxNDT_2 ((uint32_t)0x00000004) |
Definition at line 4590 of file stm32f4xx.h.
| #define DMA_SxNDT_3 ((uint32_t)0x00000008) |
Definition at line 4591 of file stm32f4xx.h.
| #define DMA_SxNDT_4 ((uint32_t)0x00000010) |
Definition at line 4592 of file stm32f4xx.h.
| #define DMA_SxNDT_5 ((uint32_t)0x00000020) |
Definition at line 4593 of file stm32f4xx.h.
| #define DMA_SxNDT_6 ((uint32_t)0x00000040) |
Definition at line 4594 of file stm32f4xx.h.
| #define DMA_SxNDT_7 ((uint32_t)0x00000080) |
Definition at line 4595 of file stm32f4xx.h.
| #define DMA_SxNDT_8 ((uint32_t)0x00000100) |
Definition at line 4596 of file stm32f4xx.h.
| #define DMA_SxNDT_9 ((uint32_t)0x00000200) |
Definition at line 4597 of file stm32f4xx.h.
| #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ |
Definition at line 11866 of file stm32f4xx.h.
| #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ |
Definition at line 11903 of file stm32f4xx.h.
| #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ |
Definition at line 11902 of file stm32f4xx.h.
| #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */ |
Definition at line 11901 of file stm32f4xx.h.
| #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ |
Definition at line 11882 of file stm32f4xx.h.
| #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ |
Definition at line 11867 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ |
Definition at line 11888 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
Definition at line 11893 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
Definition at line 11889 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
Definition at line 11890 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
Definition at line 11894 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
Definition at line 11891 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
Definition at line 11900 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
Definition at line 11897 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
Definition at line 11898 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
Definition at line 11895 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
Definition at line 11899 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
Definition at line 11896 of file stm32f4xx.h.
| #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
Definition at line 11892 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ |
Definition at line 11869 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
Definition at line 11874 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
Definition at line 11870 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
Definition at line 11871 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
Definition at line 11875 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
Definition at line 11872 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
Definition at line 11881 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
Definition at line 11878 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
Definition at line 11879 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
Definition at line 11876 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
Definition at line 11880 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
Definition at line 11877 of file stm32f4xx.h.
| #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
Definition at line 11873 of file stm32f4xx.h.
| #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
Definition at line 11883 of file stm32f4xx.h.
| #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ |
Definition at line 11884 of file stm32f4xx.h.
| #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ |
Definition at line 11885 of file stm32f4xx.h.
| #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ |
Definition at line 11886 of file stm32f4xx.h.
| #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
Definition at line 11887 of file stm32f4xx.h.
| #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ |
Definition at line 11904 of file stm32f4xx.h.
| #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ |
Definition at line 11868 of file stm32f4xx.h.
| #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ |
Definition at line 12016 of file stm32f4xx.h.
| #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ |
Definition at line 12010 of file stm32f4xx.h.
| #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ |
Definition at line 12013 of file stm32f4xx.h.
| #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ |
Definition at line 12007 of file stm32f4xx.h.
| #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ |
Definition at line 11985 of file stm32f4xx.h.
| #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ |
Definition at line 11986 of file stm32f4xx.h.
| #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ |
Definition at line 11988 of file stm32f4xx.h.
| #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ |
Definition at line 11987 of file stm32f4xx.h.
| #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ |
Definition at line 11984 of file stm32f4xx.h.
| #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ |
Definition at line 11991 of file stm32f4xx.h.
| #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ |
Definition at line 11992 of file stm32f4xx.h.
| #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ |
Definition at line 11994 of file stm32f4xx.h.
| #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ |
Definition at line 11990 of file stm32f4xx.h.
| #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ |
Definition at line 11989 of file stm32f4xx.h.
| #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ |
Definition at line 11996 of file stm32f4xx.h.
| #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ |
Definition at line 11998 of file stm32f4xx.h.
| #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ |
Definition at line 11995 of file stm32f4xx.h.
| #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ |
Definition at line 11997 of file stm32f4xx.h.
| #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ |
Definition at line 11993 of file stm32f4xx.h.
| #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ |
Definition at line 12002 of file stm32f4xx.h.
| #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ |
Definition at line 12004 of file stm32f4xx.h.
| #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ |
Definition at line 12001 of file stm32f4xx.h.
| #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ |
Definition at line 12003 of file stm32f4xx.h.
| #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ |
Definition at line 11960 of file stm32f4xx.h.
| #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ |
Definition at line 11958 of file stm32f4xx.h.
| #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ |
Definition at line 11973 of file stm32f4xx.h.
| #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ |
Definition at line 11962 of file stm32f4xx.h.
| #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ |
Definition at line 11974 of file stm32f4xx.h.
| #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ |
Definition at line 11980 of file stm32f4xx.h.
| #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ |
Definition at line 11959 of file stm32f4xx.h.
| #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ |
Definition at line 11975 of file stm32f4xx.h.
| #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
Definition at line 11979 of file stm32f4xx.h.
| #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
Definition at line 11977 of file stm32f4xx.h.
| #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
Definition at line 11976 of file stm32f4xx.h.
| #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
Definition at line 11978 of file stm32f4xx.h.
| #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ |
Definition at line 11981 of file stm32f4xx.h.
| #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ |
Definition at line 11972 of file stm32f4xx.h.
| #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ |
Definition at line 11961 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ |
Definition at line 11963 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
Definition at line 11965 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
Definition at line 11971 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
Definition at line 11966 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
Definition at line 11970 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
Definition at line 11967 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
Definition at line 11969 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
Definition at line 11968 of file stm32f4xx.h.
| #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
Definition at line 11964 of file stm32f4xx.h.
| #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ |
Definition at line 11913 of file stm32f4xx.h.
| #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ |
Definition at line 11910 of file stm32f4xx.h.
| #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ |
Definition at line 11942 of file stm32f4xx.h.
| #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ |
Definition at line 11922 of file stm32f4xx.h.
| #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ |
Definition at line 11926 of file stm32f4xx.h.
| #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ |
Definition at line 11924 of file stm32f4xx.h.
| #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ |
Definition at line 11925 of file stm32f4xx.h.
| #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ |
Definition at line 11943 of file stm32f4xx.h.
| #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ |
Definition at line 11945 of file stm32f4xx.h.
| #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ |
Definition at line 11944 of file stm32f4xx.h.
| #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ |
Definition at line 11921 of file stm32f4xx.h.
| #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ |
Definition at line 11941 of file stm32f4xx.h.
| #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ |
Definition at line 11920 of file stm32f4xx.h.
| #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ |
Definition at line 11948 of file stm32f4xx.h.
| #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ |
Definition at line 11951 of file stm32f4xx.h.
| #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ |
Definition at line 11934 of file stm32f4xx.h.
| #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ |
Definition at line 11939 of file stm32f4xx.h.
| #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ |
Definition at line 11936 of file stm32f4xx.h.
| #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ |
Definition at line 11940 of file stm32f4xx.h.
| #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ |
Definition at line 11935 of file stm32f4xx.h.
| #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ |
Definition at line 11938 of file stm32f4xx.h.
| #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ |
Definition at line 11937 of file stm32f4xx.h.
| #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ |
Definition at line 11947 of file stm32f4xx.h.
| #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ |
Definition at line 11949 of file stm32f4xx.h.
| #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ |
Definition at line 11946 of file stm32f4xx.h.
| #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ |
Definition at line 11953 of file stm32f4xx.h.
| #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ |
Definition at line 11952 of file stm32f4xx.h.
| #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ |
Definition at line 11927 of file stm32f4xx.h.
| #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ |
Definition at line 11933 of file stm32f4xx.h.
| #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ |
Definition at line 11929 of file stm32f4xx.h.
| #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ |
Definition at line 11931 of file stm32f4xx.h.
| #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ |
Definition at line 11928 of file stm32f4xx.h.
| #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ |
Definition at line 11932 of file stm32f4xx.h.
| #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ |
Definition at line 11930 of file stm32f4xx.h.
| #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ |
Definition at line 11954 of file stm32f4xx.h.
| #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ |
Definition at line 11955 of file stm32f4xx.h.
| #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ |
Definition at line 11919 of file stm32f4xx.h.
| #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ |
Definition at line 11950 of file stm32f4xx.h.
| #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ |
Definition at line 11916 of file stm32f4xx.h.
| #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ |
Definition at line 11907 of file stm32f4xx.h.
| #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ |
Definition at line 11709 of file stm32f4xx.h.
| #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ |
Definition at line 11712 of file stm32f4xx.h.
| #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ |
Definition at line 11715 of file stm32f4xx.h.
| #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
Definition at line 11724 of file stm32f4xx.h.
| #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
Definition at line 11717 of file stm32f4xx.h.
| #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
Definition at line 11718 of file stm32f4xx.h.
| #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
Definition at line 11719 of file stm32f4xx.h.
| #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
Definition at line 11722 of file stm32f4xx.h.
| #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
Definition at line 11721 of file stm32f4xx.h.
| #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
Definition at line 11720 of file stm32f4xx.h.
| #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ |
Definition at line 11723 of file stm32f4xx.h.
| #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ |
Definition at line 11716 of file stm32f4xx.h.
| #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ |
Definition at line 11727 of file stm32f4xx.h.
| #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ |
Definition at line 11730 of file stm32f4xx.h.
| #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
Definition at line 11739 of file stm32f4xx.h.
| #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
Definition at line 11732 of file stm32f4xx.h.
| #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
Definition at line 11733 of file stm32f4xx.h.
| #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
Definition at line 11734 of file stm32f4xx.h.
| #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
Definition at line 11737 of file stm32f4xx.h.
| #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
Definition at line 11736 of file stm32f4xx.h.
| #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
Definition at line 11735 of file stm32f4xx.h.
| #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
Definition at line 11738 of file stm32f4xx.h.
| #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ |
Definition at line 11731 of file stm32f4xx.h.
| #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ |
Definition at line 11742 of file stm32f4xx.h.
| #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ |
Definition at line 11745 of file stm32f4xx.h.
| #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ |
Definition at line 11754 of file stm32f4xx.h.
| #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
Definition at line 11747 of file stm32f4xx.h.
| #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
Definition at line 11748 of file stm32f4xx.h.
| #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
Definition at line 11749 of file stm32f4xx.h.
| #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
Definition at line 11752 of file stm32f4xx.h.
| #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
Definition at line 11751 of file stm32f4xx.h.
| #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
Definition at line 11750 of file stm32f4xx.h.
| #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
Definition at line 11753 of file stm32f4xx.h.
| #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ |
Definition at line 11746 of file stm32f4xx.h.
| #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ |
Definition at line 11757 of file stm32f4xx.h.
| #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ |
Definition at line 11610 of file stm32f4xx.h.
| #define ETH_MACCR_BL |
Definition at line 11611 of file stm32f4xx.h.
| #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ |
Definition at line 11615 of file stm32f4xx.h.
| #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ |
Definition at line 11612 of file stm32f4xx.h.
| #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ |
Definition at line 11614 of file stm32f4xx.h.
| #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ |
Definition at line 11613 of file stm32f4xx.h.
| #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ |
Definition at line 11603 of file stm32f4xx.h.
| #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ |
Definition at line 11616 of file stm32f4xx.h.
| #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ |
Definition at line 11607 of file stm32f4xx.h.
| #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ |
Definition at line 11604 of file stm32f4xx.h.
| #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ |
Definition at line 11594 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ |
Definition at line 11602 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ |
Definition at line 11601 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ |
Definition at line 11600 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ |
Definition at line 11599 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ |
Definition at line 11598 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ |
Definition at line 11597 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ |
Definition at line 11596 of file stm32f4xx.h.
| #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ |
Definition at line 11595 of file stm32f4xx.h.
| #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ |
Definition at line 11608 of file stm32f4xx.h.
| #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ |
Definition at line 11593 of file stm32f4xx.h.
| #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ |
Definition at line 11606 of file stm32f4xx.h.
| #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ |
Definition at line 11609 of file stm32f4xx.h.
| #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ |
Definition at line 11618 of file stm32f4xx.h.
| #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ |
Definition at line 11605 of file stm32f4xx.h.
| #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ |
Definition at line 11617 of file stm32f4xx.h.
| #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ |
Definition at line 11592 of file stm32f4xx.h.
| #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ |
Definition at line 11668 of file stm32f4xx.h.
| #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ |
Definition at line 11660 of file stm32f4xx.h.
| #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ |
Definition at line 11663 of file stm32f4xx.h.
| #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ |
Definition at line 11664 of file stm32f4xx.h.
| #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ |
Definition at line 11662 of file stm32f4xx.h.
| #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ |
Definition at line 11661 of file stm32f4xx.h.
| #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ |
Definition at line 11658 of file stm32f4xx.h.
| #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ |
Definition at line 11666 of file stm32f4xx.h.
| #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ |
Definition at line 11667 of file stm32f4xx.h.
| #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ |
Definition at line 11665 of file stm32f4xx.h.
| #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ |
Definition at line 11659 of file stm32f4xx.h.
| #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ |
Definition at line 11629 of file stm32f4xx.h.
| #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ |
Definition at line 11631 of file stm32f4xx.h.
| #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ |
Definition at line 11632 of file stm32f4xx.h.
| #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ |
Definition at line 11622 of file stm32f4xx.h.
| #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ |
Definition at line 11633 of file stm32f4xx.h.
| #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ |
Definition at line 11630 of file stm32f4xx.h.
| #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ |
Definition at line 11625 of file stm32f4xx.h.
| #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ |
Definition at line 11626 of file stm32f4xx.h.
| #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ |
Definition at line 11627 of file stm32f4xx.h.
| #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ |
Definition at line 11628 of file stm32f4xx.h.
| #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ |
Definition at line 11634 of file stm32f4xx.h.
| #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ |
Definition at line 11621 of file stm32f4xx.h.
| #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ |
Definition at line 11623 of file stm32f4xx.h.
| #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ |
Definition at line 11624 of file stm32f4xx.h.
| #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ |
Definition at line 11637 of file stm32f4xx.h.
| #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ |
Definition at line 11640 of file stm32f4xx.h.
| #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ |
Definition at line 11706 of file stm32f4xx.h.
| #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ |
Definition at line 11705 of file stm32f4xx.h.
| #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ |
Definition at line 11645 of file stm32f4xx.h.
| #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ |
Definition at line 11650 of file stm32f4xx.h.
| #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
Definition at line 11648 of file stm32f4xx.h.
| #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
Definition at line 11649 of file stm32f4xx.h.
| #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ |
Definition at line 11646 of file stm32f4xx.h.
| #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ |
Definition at line 11647 of file stm32f4xx.h.
| #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ |
Definition at line 11652 of file stm32f4xx.h.
| #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ |
Definition at line 11644 of file stm32f4xx.h.
| #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ |
Definition at line 11651 of file stm32f4xx.h.
| #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ |
Definition at line 11643 of file stm32f4xx.h.
| #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ |
Definition at line 11655 of file stm32f4xx.h.
| #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ |
Definition at line 11690 of file stm32f4xx.h.
| #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ |
Definition at line 11694 of file stm32f4xx.h.
| #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ |
Definition at line 11692 of file stm32f4xx.h.
| #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ |
Definition at line 11695 of file stm32f4xx.h.
| #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ |
Definition at line 11693 of file stm32f4xx.h.
| #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ |
Definition at line 11689 of file stm32f4xx.h.
| #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ |
Definition at line 11691 of file stm32f4xx.h.
| #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ |
Definition at line 11675 of file stm32f4xx.h.
| #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ |
Definition at line 11701 of file stm32f4xx.h.
| #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ |
Definition at line 11699 of file stm32f4xx.h.
| #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ |
Definition at line 11700 of file stm32f4xx.h.
| #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ |
Definition at line 11702 of file stm32f4xx.h.
| #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ |
Definition at line 11698 of file stm32f4xx.h.
| #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ |
Definition at line 11671 of file stm32f4xx.h.
| #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ |
Definition at line 11672 of file stm32f4xx.h.
| #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ |
Definition at line 11769 of file stm32f4xx.h.
| #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ |
Definition at line 11768 of file stm32f4xx.h.
| #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ |
Definition at line 11766 of file stm32f4xx.h.
| #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */ |
Definition at line 11764 of file stm32f4xx.h.
| #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */ |
Definition at line 11765 of file stm32f4xx.h.
| #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ |
Definition at line 11767 of file stm32f4xx.h.
| #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ |
Definition at line 11804 of file stm32f4xx.h.
| #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ |
Definition at line 11801 of file stm32f4xx.h.
| #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ |
Definition at line 11807 of file stm32f4xx.h.
| #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
Definition at line 11783 of file stm32f4xx.h.
| #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
Definition at line 11784 of file stm32f4xx.h.
| #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
Definition at line 11782 of file stm32f4xx.h.
| #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ |
Definition at line 11773 of file stm32f4xx.h.
| #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ |
Definition at line 11774 of file stm32f4xx.h.
| #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ |
Definition at line 11772 of file stm32f4xx.h.
| #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ |
Definition at line 11798 of file stm32f4xx.h.
| #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
Definition at line 11795 of file stm32f4xx.h.
| #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
Definition at line 11792 of file stm32f4xx.h.
| #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
Definition at line 11787 of file stm32f4xx.h.
| #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
Definition at line 11788 of file stm32f4xx.h.
| #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
Definition at line 11789 of file stm32f4xx.h.
| #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ |
Definition at line 11778 of file stm32f4xx.h.
| #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ |
Definition at line 11777 of file stm32f4xx.h.
| #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ |
Definition at line 11779 of file stm32f4xx.h.
| #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ |
Definition at line 11832 of file stm32f4xx.h.
| #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ |
Definition at line 11849 of file stm32f4xx.h.
| #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ |
Definition at line 11824 of file stm32f4xx.h.
| #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */ |
Definition at line 11814 of file stm32f4xx.h.
| #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ |
Definition at line 11829 of file stm32f4xx.h.
| #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ |
Definition at line 11828 of file stm32f4xx.h.
| #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ |
Definition at line 11825 of file stm32f4xx.h.
| #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ |
Definition at line 11827 of file stm32f4xx.h.
| #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ |
Definition at line 11826 of file stm32f4xx.h.
| #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ |
Definition at line 11835 of file stm32f4xx.h.
| #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ |
Definition at line 11842 of file stm32f4xx.h.
| #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ |
Definition at line 11838 of file stm32f4xx.h.
| #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ |
Definition at line 11839 of file stm32f4xx.h.
| #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ |
Definition at line 11845 of file stm32f4xx.h.
| #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ |
Definition at line 11846 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ |
Definition at line 11820 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */ |
Definition at line 11822 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */ |
Definition at line 11816 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ |
Definition at line 11817 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ |
Definition at line 11818 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */ |
Definition at line 11815 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */ |
Definition at line 11859 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ |
Definition at line 11819 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */ |
Definition at line 11821 of file stm32f4xx.h.
| #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */ |
Definition at line 11858 of file stm32f4xx.h.
| #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ |
Definition at line 11852 of file stm32f4xx.h.
| #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ |
Definition at line 11855 of file stm32f4xx.h.
| #define EXTI_EMR_MR0 ((uint32_t)0x00000001) |
Event Mask on line 0
Definition at line 4906 of file stm32f4xx.h.
| #define EXTI_EMR_MR1 ((uint32_t)0x00000002) |
Event Mask on line 1
Definition at line 4907 of file stm32f4xx.h.
| #define EXTI_EMR_MR10 ((uint32_t)0x00000400) |
Event Mask on line 10
Definition at line 4916 of file stm32f4xx.h.
| #define EXTI_EMR_MR11 ((uint32_t)0x00000800) |
Event Mask on line 11
Definition at line 4917 of file stm32f4xx.h.
| #define EXTI_EMR_MR12 ((uint32_t)0x00001000) |
Event Mask on line 12
Definition at line 4918 of file stm32f4xx.h.
| #define EXTI_EMR_MR13 ((uint32_t)0x00002000) |
Event Mask on line 13
Definition at line 4919 of file stm32f4xx.h.
| #define EXTI_EMR_MR14 ((uint32_t)0x00004000) |
Event Mask on line 14
Definition at line 4920 of file stm32f4xx.h.
| #define EXTI_EMR_MR15 ((uint32_t)0x00008000) |
Event Mask on line 15
Definition at line 4921 of file stm32f4xx.h.
| #define EXTI_EMR_MR16 ((uint32_t)0x00010000) |
Event Mask on line 16
Definition at line 4922 of file stm32f4xx.h.
| #define EXTI_EMR_MR17 ((uint32_t)0x00020000) |
Event Mask on line 17
Definition at line 4923 of file stm32f4xx.h.
| #define EXTI_EMR_MR18 ((uint32_t)0x00040000) |
Event Mask on line 18
Definition at line 4924 of file stm32f4xx.h.
| #define EXTI_EMR_MR19 ((uint32_t)0x00080000) |
Event Mask on line 19
Definition at line 4925 of file stm32f4xx.h.
| #define EXTI_EMR_MR2 ((uint32_t)0x00000004) |
Event Mask on line 2
Definition at line 4908 of file stm32f4xx.h.
| #define EXTI_EMR_MR23 ((uint32_t)0x00800000) |
Event Mask on line 19
Definition at line 4926 of file stm32f4xx.h.
| #define EXTI_EMR_MR3 ((uint32_t)0x00000008) |
Event Mask on line 3
Definition at line 4909 of file stm32f4xx.h.
| #define EXTI_EMR_MR4 ((uint32_t)0x00000010) |
Event Mask on line 4
Definition at line 4910 of file stm32f4xx.h.
| #define EXTI_EMR_MR5 ((uint32_t)0x00000020) |
Event Mask on line 5
Definition at line 4911 of file stm32f4xx.h.
| #define EXTI_EMR_MR6 ((uint32_t)0x00000040) |
Event Mask on line 6
Definition at line 4912 of file stm32f4xx.h.
| #define EXTI_EMR_MR7 ((uint32_t)0x00000080) |
Event Mask on line 7
Definition at line 4913 of file stm32f4xx.h.
| #define EXTI_EMR_MR8 ((uint32_t)0x00000100) |
Event Mask on line 8
Definition at line 4914 of file stm32f4xx.h.
| #define EXTI_EMR_MR9 ((uint32_t)0x00000200) |
Event Mask on line 9
Definition at line 4915 of file stm32f4xx.h.
| #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
Falling trigger event configuration bit of line 0
Definition at line 4952 of file stm32f4xx.h.
| #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
Falling trigger event configuration bit of line 1
Definition at line 4953 of file stm32f4xx.h.
| #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
Falling trigger event configuration bit of line 10
Definition at line 4962 of file stm32f4xx.h.
| #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
Falling trigger event configuration bit of line 11
Definition at line 4963 of file stm32f4xx.h.
| #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
Falling trigger event configuration bit of line 12
Definition at line 4964 of file stm32f4xx.h.
| #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
Falling trigger event configuration bit of line 13
Definition at line 4965 of file stm32f4xx.h.
| #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
Falling trigger event configuration bit of line 14
Definition at line 4966 of file stm32f4xx.h.
| #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
Falling trigger event configuration bit of line 15
Definition at line 4967 of file stm32f4xx.h.
| #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
Falling trigger event configuration bit of line 16
Definition at line 4968 of file stm32f4xx.h.
| #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
Falling trigger event configuration bit of line 17
Definition at line 4969 of file stm32f4xx.h.
| #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
Falling trigger event configuration bit of line 18
Definition at line 4970 of file stm32f4xx.h.
| #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
Falling trigger event configuration bit of line 19
Definition at line 4971 of file stm32f4xx.h.
| #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
Falling trigger event configuration bit of line 2
Definition at line 4954 of file stm32f4xx.h.
| #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) |
Falling trigger event configuration bit of line 23
Definition at line 4972 of file stm32f4xx.h.
| #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
Falling trigger event configuration bit of line 3
Definition at line 4955 of file stm32f4xx.h.
| #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
Falling trigger event configuration bit of line 4
Definition at line 4956 of file stm32f4xx.h.
| #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
Falling trigger event configuration bit of line 5
Definition at line 4957 of file stm32f4xx.h.
| #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
Falling trigger event configuration bit of line 6
Definition at line 4958 of file stm32f4xx.h.
| #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
Falling trigger event configuration bit of line 7
Definition at line 4959 of file stm32f4xx.h.
| #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
Falling trigger event configuration bit of line 8
Definition at line 4960 of file stm32f4xx.h.
| #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
Falling trigger event configuration bit of line 9
Definition at line 4961 of file stm32f4xx.h.
| #define EXTI_IMR_MR0 ((uint32_t)0x00000001) |
Interrupt Mask on line 0
Definition at line 4883 of file stm32f4xx.h.
| #define EXTI_IMR_MR1 ((uint32_t)0x00000002) |
Interrupt Mask on line 1
Definition at line 4884 of file stm32f4xx.h.
| #define EXTI_IMR_MR10 ((uint32_t)0x00000400) |
Interrupt Mask on line 10
Definition at line 4893 of file stm32f4xx.h.
| #define EXTI_IMR_MR11 ((uint32_t)0x00000800) |
Interrupt Mask on line 11
Definition at line 4894 of file stm32f4xx.h.
| #define EXTI_IMR_MR12 ((uint32_t)0x00001000) |
Interrupt Mask on line 12
Definition at line 4895 of file stm32f4xx.h.
| #define EXTI_IMR_MR13 ((uint32_t)0x00002000) |
Interrupt Mask on line 13
Definition at line 4896 of file stm32f4xx.h.
| #define EXTI_IMR_MR14 ((uint32_t)0x00004000) |
Interrupt Mask on line 14
Definition at line 4897 of file stm32f4xx.h.
| #define EXTI_IMR_MR15 ((uint32_t)0x00008000) |
Interrupt Mask on line 15
Definition at line 4898 of file stm32f4xx.h.
| #define EXTI_IMR_MR16 ((uint32_t)0x00010000) |
Interrupt Mask on line 16
Definition at line 4899 of file stm32f4xx.h.
| #define EXTI_IMR_MR17 ((uint32_t)0x00020000) |
Interrupt Mask on line 17
Definition at line 4900 of file stm32f4xx.h.
| #define EXTI_IMR_MR18 ((uint32_t)0x00040000) |
Interrupt Mask on line 18
Definition at line 4901 of file stm32f4xx.h.
| #define EXTI_IMR_MR19 ((uint32_t)0x00080000) |
Interrupt Mask on line 19
Definition at line 4902 of file stm32f4xx.h.
| #define EXTI_IMR_MR2 ((uint32_t)0x00000004) |
Interrupt Mask on line 2
Definition at line 4885 of file stm32f4xx.h.
| #define EXTI_IMR_MR23 ((uint32_t)0x00800000) |
Interrupt Mask on line 23
Definition at line 4903 of file stm32f4xx.h.
| #define EXTI_IMR_MR3 ((uint32_t)0x00000008) |
Interrupt Mask on line 3
Definition at line 4886 of file stm32f4xx.h.
| #define EXTI_IMR_MR4 ((uint32_t)0x00000010) |
Interrupt Mask on line 4
Definition at line 4887 of file stm32f4xx.h.
| #define EXTI_IMR_MR5 ((uint32_t)0x00000020) |
Interrupt Mask on line 5
Definition at line 4888 of file stm32f4xx.h.
| #define EXTI_IMR_MR6 ((uint32_t)0x00000040) |
Interrupt Mask on line 6
Definition at line 4889 of file stm32f4xx.h.
| #define EXTI_IMR_MR7 ((uint32_t)0x00000080) |
Interrupt Mask on line 7
Definition at line 4890 of file stm32f4xx.h.
| #define EXTI_IMR_MR8 ((uint32_t)0x00000100) |
Interrupt Mask on line 8
Definition at line 4891 of file stm32f4xx.h.
| #define EXTI_IMR_MR9 ((uint32_t)0x00000200) |
Interrupt Mask on line 9
Definition at line 4892 of file stm32f4xx.h.
| #define EXTI_PR_PR0 ((uint32_t)0x00000001) |
Pending bit for line 0
Definition at line 4998 of file stm32f4xx.h.
| #define EXTI_PR_PR1 ((uint32_t)0x00000002) |
Pending bit for line 1
Definition at line 4999 of file stm32f4xx.h.
| #define EXTI_PR_PR10 ((uint32_t)0x00000400) |
Pending bit for line 10
Definition at line 5008 of file stm32f4xx.h.
| #define EXTI_PR_PR11 ((uint32_t)0x00000800) |
Pending bit for line 11
Definition at line 5009 of file stm32f4xx.h.
| #define EXTI_PR_PR12 ((uint32_t)0x00001000) |
Pending bit for line 12
Definition at line 5010 of file stm32f4xx.h.
| #define EXTI_PR_PR13 ((uint32_t)0x00002000) |
Pending bit for line 13
Definition at line 5011 of file stm32f4xx.h.
| #define EXTI_PR_PR14 ((uint32_t)0x00004000) |
Pending bit for line 14
Definition at line 5012 of file stm32f4xx.h.
| #define EXTI_PR_PR15 ((uint32_t)0x00008000) |
Pending bit for line 15
Definition at line 5013 of file stm32f4xx.h.
| #define EXTI_PR_PR16 ((uint32_t)0x00010000) |
Pending bit for line 16
Definition at line 5014 of file stm32f4xx.h.
| #define EXTI_PR_PR17 ((uint32_t)0x00020000) |
Pending bit for line 17
Definition at line 5015 of file stm32f4xx.h.
| #define EXTI_PR_PR18 ((uint32_t)0x00040000) |
Pending bit for line 18
Definition at line 5016 of file stm32f4xx.h.
| #define EXTI_PR_PR19 ((uint32_t)0x00080000) |
Pending bit for line 19
Definition at line 5017 of file stm32f4xx.h.
| #define EXTI_PR_PR2 ((uint32_t)0x00000004) |
Pending bit for line 2
Definition at line 5000 of file stm32f4xx.h.
| #define EXTI_PR_PR23 ((uint32_t)0x00800000) |
Pending bit for line 23
Definition at line 5018 of file stm32f4xx.h.
| #define EXTI_PR_PR3 ((uint32_t)0x00000008) |
Pending bit for line 3
Definition at line 5001 of file stm32f4xx.h.
| #define EXTI_PR_PR4 ((uint32_t)0x00000010) |
Pending bit for line 4
Definition at line 5002 of file stm32f4xx.h.
| #define EXTI_PR_PR5 ((uint32_t)0x00000020) |
Pending bit for line 5
Definition at line 5003 of file stm32f4xx.h.
| #define EXTI_PR_PR6 ((uint32_t)0x00000040) |
Pending bit for line 6
Definition at line 5004 of file stm32f4xx.h.
| #define EXTI_PR_PR7 ((uint32_t)0x00000080) |
Pending bit for line 7
Definition at line 5005 of file stm32f4xx.h.
| #define EXTI_PR_PR8 ((uint32_t)0x00000100) |
Pending bit for line 8
Definition at line 5006 of file stm32f4xx.h.
| #define EXTI_PR_PR9 ((uint32_t)0x00000200) |
Pending bit for line 9
Definition at line 5007 of file stm32f4xx.h.
| #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
Rising trigger event configuration bit of line 0
Definition at line 4929 of file stm32f4xx.h.
| #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
Rising trigger event configuration bit of line 1
Definition at line 4930 of file stm32f4xx.h.
| #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
Rising trigger event configuration bit of line 10
Definition at line 4939 of file stm32f4xx.h.
| #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
Rising trigger event configuration bit of line 11
Definition at line 4940 of file stm32f4xx.h.
| #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
Rising trigger event configuration bit of line 12
Definition at line 4941 of file stm32f4xx.h.
| #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
Rising trigger event configuration bit of line 13
Definition at line 4942 of file stm32f4xx.h.
| #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
Rising trigger event configuration bit of line 14
Definition at line 4943 of file stm32f4xx.h.
| #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
Rising trigger event configuration bit of line 15
Definition at line 4944 of file stm32f4xx.h.
| #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
Rising trigger event configuration bit of line 16
Definition at line 4945 of file stm32f4xx.h.
| #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
Rising trigger event configuration bit of line 17
Definition at line 4946 of file stm32f4xx.h.
| #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
Rising trigger event configuration bit of line 18
Definition at line 4947 of file stm32f4xx.h.
| #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
Rising trigger event configuration bit of line 19
Definition at line 4948 of file stm32f4xx.h.
| #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
Rising trigger event configuration bit of line 2
Definition at line 4931 of file stm32f4xx.h.
| #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) |
Rising trigger event configuration bit of line 23
Definition at line 4949 of file stm32f4xx.h.
| #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
Rising trigger event configuration bit of line 3
Definition at line 4932 of file stm32f4xx.h.
| #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
Rising trigger event configuration bit of line 4
Definition at line 4933 of file stm32f4xx.h.
| #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
Rising trigger event configuration bit of line 5
Definition at line 4934 of file stm32f4xx.h.
| #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
Rising trigger event configuration bit of line 6
Definition at line 4935 of file stm32f4xx.h.
| #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
Rising trigger event configuration bit of line 7
Definition at line 4936 of file stm32f4xx.h.
| #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
Rising trigger event configuration bit of line 8
Definition at line 4937 of file stm32f4xx.h.
| #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
Rising trigger event configuration bit of line 9
Definition at line 4938 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
Software Interrupt on line 0
Definition at line 4975 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
Software Interrupt on line 1
Definition at line 4976 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
Software Interrupt on line 10
Definition at line 4985 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
Software Interrupt on line 11
Definition at line 4986 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
Software Interrupt on line 12
Definition at line 4987 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
Software Interrupt on line 13
Definition at line 4988 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
Software Interrupt on line 14
Definition at line 4989 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
Software Interrupt on line 15
Definition at line 4990 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
Software Interrupt on line 16
Definition at line 4991 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
Software Interrupt on line 17
Definition at line 4992 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
Software Interrupt on line 18
Definition at line 4993 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
Software Interrupt on line 19
Definition at line 4994 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
Software Interrupt on line 2
Definition at line 4977 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) |
Software Interrupt on line 23
Definition at line 4995 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
Software Interrupt on line 3
Definition at line 4978 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
Software Interrupt on line 4
Definition at line 4979 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
Software Interrupt on line 5
Definition at line 4980 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
Software Interrupt on line 6
Definition at line 4981 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
Software Interrupt on line 7
Definition at line 4982 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
Software Interrupt on line 8
Definition at line 4983 of file stm32f4xx.h.
| #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
Software Interrupt on line 9
Definition at line 4984 of file stm32f4xx.h.
| #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) |
Definition at line 5049 of file stm32f4xx.h.
| #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03) |
Definition at line 5050 of file stm32f4xx.h.
| #define FLASH_ACR_DCEN ((uint32_t)0x00000400) |
Definition at line 5046 of file stm32f4xx.h.
Referenced by FLASH_DataCacheCmd(), and SetSysClock().
| #define FLASH_ACR_DCRST ((uint32_t)0x00001000) |
Definition at line 5048 of file stm32f4xx.h.
Referenced by FLASH_DataCacheReset().
| #define FLASH_ACR_ICEN ((uint32_t)0x00000200) |
Definition at line 5045 of file stm32f4xx.h.
Referenced by FLASH_InstructionCacheCmd(), and SetSysClock().
| #define FLASH_ACR_ICRST ((uint32_t)0x00000800) |
Definition at line 5047 of file stm32f4xx.h.
Referenced by FLASH_InstructionCacheReset().
| #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F) |
Definition at line 5026 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000) |
Definition at line 5027 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A) |
Definition at line 5037 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B) |
Definition at line 5038 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C) |
Definition at line 5039 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D) |
Definition at line 5040 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E) |
Definition at line 5041 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F) |
Definition at line 5042 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001) |
Definition at line 5028 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002) |
Definition at line 5029 of file stm32f4xx.h.
Referenced by SetSysClock().
| #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003) |
Definition at line 5030 of file stm32f4xx.h.
Referenced by SetSysClock().
| #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004) |
Definition at line 5031 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005) |
Definition at line 5032 of file stm32f4xx.h.
Referenced by SetSysClock().
| #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006) |
Definition at line 5033 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007) |
Definition at line 5034 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008) |
Definition at line 5035 of file stm32f4xx.h.
| #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009) |
Definition at line 5036 of file stm32f4xx.h.
| #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100) |
Definition at line 5044 of file stm32f4xx.h.
Referenced by FLASH_PrefetchBufferCmd(), and SetSysClock().
| #define FLASH_CR_EOPIE ((uint32_t)0x01000000) |
Definition at line 5077 of file stm32f4xx.h.
| #define FLASH_CR_LOCK ((uint32_t)0x80000000) |
Definition at line 5078 of file stm32f4xx.h.
Referenced by FLASH_Lock(), and FLASH_Unlock().
| #define FLASH_CR_MER ((uint32_t)0x00000004) |
Definition at line 5064 of file stm32f4xx.h.
Referenced by FLASH_EraseAllSectors().
| #define FLASH_CR_MER1 FLASH_CR_MER |
Definition at line 5065 of file stm32f4xx.h.
Referenced by FLASH_EraseAllBank1Sectors(), and FLASH_EraseAllSectors().
| #define FLASH_CR_MER2 ((uint32_t)0x00008000) |
Definition at line 5075 of file stm32f4xx.h.
Referenced by FLASH_EraseAllBank2Sectors(), and FLASH_EraseAllSectors().
| #define FLASH_CR_PG ((uint32_t)0x00000001) |
Definition at line 5062 of file stm32f4xx.h.
Referenced by FLASH_ProgramByte(), FLASH_ProgramDoubleWord(), FLASH_ProgramHalfWord(), and FLASH_ProgramWord().
| #define FLASH_CR_PSIZE ((uint32_t)0x00000300) |
Definition at line 5072 of file stm32f4xx.h.
| #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100) |
Definition at line 5073 of file stm32f4xx.h.
| #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200) |
Definition at line 5074 of file stm32f4xx.h.
| #define FLASH_CR_SER ((uint32_t)0x00000002) |
Definition at line 5063 of file stm32f4xx.h.
Referenced by FLASH_EraseSector().
| #define FLASH_CR_SNB ((uint32_t)0x000000F8) |
Definition at line 5066 of file stm32f4xx.h.
| #define FLASH_CR_SNB_0 ((uint32_t)0x00000008) |
Definition at line 5067 of file stm32f4xx.h.
| #define FLASH_CR_SNB_1 ((uint32_t)0x00000010) |
Definition at line 5068 of file stm32f4xx.h.
| #define FLASH_CR_SNB_2 ((uint32_t)0x00000020) |
Definition at line 5069 of file stm32f4xx.h.
| #define FLASH_CR_SNB_3 ((uint32_t)0x00000040) |
Definition at line 5070 of file stm32f4xx.h.
| #define FLASH_CR_SNB_4 ((uint32_t)0x00000040) |
Definition at line 5071 of file stm32f4xx.h.
| #define FLASH_CR_STRT ((uint32_t)0x00010000) |
Definition at line 5076 of file stm32f4xx.h.
Referenced by FLASH_EraseAllBank1Sectors(), FLASH_EraseAllBank2Sectors(), FLASH_EraseAllSectors(), and FLASH_EraseSector().
| #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000) |
Definition at line 5118 of file stm32f4xx.h.
| #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000) |
Definition at line 5119 of file stm32f4xx.h.
| #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000) |
Definition at line 5120 of file stm32f4xx.h.
| #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000) |
Definition at line 5129 of file stm32f4xx.h.
| #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000) |
Definition at line 5130 of file stm32f4xx.h.
| #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000) |
Definition at line 5121 of file stm32f4xx.h.
| #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000) |
Definition at line 5122 of file stm32f4xx.h.
| #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000) |
Definition at line 5123 of file stm32f4xx.h.
| #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000) |
Definition at line 5124 of file stm32f4xx.h.
| #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000) |
Definition at line 5125 of file stm32f4xx.h.
| #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000) |
Definition at line 5126 of file stm32f4xx.h.
| #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000) |
Definition at line 5127 of file stm32f4xx.h.
| #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000) |
Definition at line 5128 of file stm32f4xx.h.
| #define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010) |
Definition at line 5086 of file stm32f4xx.h.
Referenced by FLASH_OB_BootConfig().
| #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C) |
Definition at line 5085 of file stm32f4xx.h.
Referenced by FLASH_OB_BORConfig().
| #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004) |
Definition at line 5083 of file stm32f4xx.h.
| #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008) |
Definition at line 5084 of file stm32f4xx.h.
| #define FLASH_OPTCR_DB1M ((uint32_t)0x40000000) |
Definition at line 5114 of file stm32f4xx.h.
| #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080) |
Definition at line 5090 of file stm32f4xx.h.
| #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040) |
Definition at line 5089 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000) |
Definition at line 5100 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000) |
Definition at line 5101 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000) |
Definition at line 5102 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000) |
Definition at line 5111 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000) |
Definition at line 5112 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000) |
Definition at line 5103 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000) |
Definition at line 5104 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000) |
Definition at line 5105 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000) |
Definition at line 5106 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000) |
Definition at line 5107 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000) |
Definition at line 5108 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000) |
Definition at line 5109 of file stm32f4xx.h.
| #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000) |
Definition at line 5110 of file stm32f4xx.h.
| #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001) |
Definition at line 5081 of file stm32f4xx.h.
Referenced by FLASH_OB_Lock(), and FLASH_OB_Unlock().
| #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002) |
Definition at line 5082 of file stm32f4xx.h.
Referenced by FLASH_OB_Launch().
| #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00) |
Definition at line 5091 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100) |
Definition at line 5092 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200) |
Definition at line 5093 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400) |
Definition at line 5094 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800) |
Definition at line 5095 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000) |
Definition at line 5096 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000) |
Definition at line 5097 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000) |
Definition at line 5098 of file stm32f4xx.h.
| #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000) |
Definition at line 5099 of file stm32f4xx.h.
| #define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000) |
Definition at line 5115 of file stm32f4xx.h.
| #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020) |
Definition at line 5088 of file stm32f4xx.h.
| #define FLASH_SR_BSY ((uint32_t)0x00010000) |
Definition at line 5059 of file stm32f4xx.h.
| #define FLASH_SR_EOP ((uint32_t)0x00000001) |
Definition at line 5053 of file stm32f4xx.h.
| #define FLASH_SR_PGAERR ((uint32_t)0x00000020) |
Definition at line 5056 of file stm32f4xx.h.
| #define FLASH_SR_PGPERR ((uint32_t)0x00000040) |
Definition at line 5057 of file stm32f4xx.h.
| #define FLASH_SR_PGSERR ((uint32_t)0x00000080) |
Definition at line 5058 of file stm32f4xx.h.
| #define FLASH_SR_SOP ((uint32_t)0x00000002) |
Definition at line 5054 of file stm32f4xx.h.
| #define FLASH_SR_WRPERR ((uint32_t)0x00000010) |
Definition at line 5055 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) |
Definition at line 7215 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) |
Definition at line 7216 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) |
Definition at line 7225 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) |
Definition at line 7226 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) |
Definition at line 7227 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) |
Definition at line 7228 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) |
Definition at line 7229 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) |
Definition at line 7230 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) |
Definition at line 7217 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) |
Definition at line 7218 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) |
Definition at line 7219 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) |
Definition at line 7220 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) |
Definition at line 7221 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) |
Definition at line 7222 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) |
Definition at line 7223 of file stm32f4xx.h.
| #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) |
Definition at line 7224 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) |
Definition at line 7199 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) |
Definition at line 7200 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) |
Definition at line 7209 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) |
Definition at line 7210 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) |
Definition at line 7211 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) |
Definition at line 7212 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) |
Definition at line 7213 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) |
Definition at line 7214 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) |
Definition at line 7201 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) |
Definition at line 7202 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) |
Definition at line 7203 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) |
Definition at line 7204 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) |
Definition at line 7205 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) |
Definition at line 7206 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) |
Definition at line 7207 of file stm32f4xx.h.
| #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) |
Definition at line 7208 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001) |
Definition at line 7129 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002) |
Definition at line 7130 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400) |
Definition at line 7139 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800) |
Definition at line 7140 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000) |
Definition at line 7141 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000) |
Definition at line 7142 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000) |
Definition at line 7143 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000) |
Definition at line 7144 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004) |
Definition at line 7131 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008) |
Definition at line 7132 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010) |
Definition at line 7133 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020) |
Definition at line 7134 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040) |
Definition at line 7135 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080) |
Definition at line 7136 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100) |
Definition at line 7137 of file stm32f4xx.h.
| #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200) |
Definition at line 7138 of file stm32f4xx.h.
| #define GPIO_MODER_MODER0 ((uint32_t)0x00000003) |
Definition at line 6916 of file stm32f4xx.h.
Referenced by GPIO_Init().
| #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) |
Definition at line 6917 of file stm32f4xx.h.
| #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) |
Definition at line 6918 of file stm32f4xx.h.
| #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) |
Definition at line 6920 of file stm32f4xx.h.
| #define GPIO_MODER_MODER10 ((uint32_t)0x00300000) |
Definition at line 6956 of file stm32f4xx.h.
| #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) |
Definition at line 6957 of file stm32f4xx.h.
| #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) |
Definition at line 6958 of file stm32f4xx.h.
| #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) |
Definition at line 6960 of file stm32f4xx.h.
| #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) |
Definition at line 6961 of file stm32f4xx.h.
| #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) |
Definition at line 6962 of file stm32f4xx.h.
| #define GPIO_MODER_MODER12 ((uint32_t)0x03000000) |
Definition at line 6964 of file stm32f4xx.h.
| #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) |
Definition at line 6965 of file stm32f4xx.h.
| #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) |
Definition at line 6966 of file stm32f4xx.h.
| #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) |
Definition at line 6968 of file stm32f4xx.h.
| #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) |
Definition at line 6969 of file stm32f4xx.h.
| #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) |
Definition at line 6970 of file stm32f4xx.h.
| #define GPIO_MODER_MODER14 ((uint32_t)0x30000000) |
Definition at line 6972 of file stm32f4xx.h.
| #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) |
Definition at line 6973 of file stm32f4xx.h.
| #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) |
Definition at line 6974 of file stm32f4xx.h.
| #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) |
Definition at line 6976 of file stm32f4xx.h.
| #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) |
Definition at line 6977 of file stm32f4xx.h.
| #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) |
Definition at line 6978 of file stm32f4xx.h.
| #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) |
Definition at line 6921 of file stm32f4xx.h.
| #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) |
Definition at line 6922 of file stm32f4xx.h.
| #define GPIO_MODER_MODER2 ((uint32_t)0x00000030) |
Definition at line 6924 of file stm32f4xx.h.
| #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) |
Definition at line 6925 of file stm32f4xx.h.
| #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) |
Definition at line 6926 of file stm32f4xx.h.
| #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) |
Definition at line 6928 of file stm32f4xx.h.
| #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) |
Definition at line 6929 of file stm32f4xx.h.
| #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) |
Definition at line 6930 of file stm32f4xx.h.
| #define GPIO_MODER_MODER4 ((uint32_t)0x00000300) |
Definition at line 6932 of file stm32f4xx.h.
| #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) |
Definition at line 6933 of file stm32f4xx.h.
| #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) |
Definition at line 6934 of file stm32f4xx.h.
| #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) |
Definition at line 6936 of file stm32f4xx.h.
| #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) |
Definition at line 6937 of file stm32f4xx.h.
| #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) |
Definition at line 6938 of file stm32f4xx.h.
| #define GPIO_MODER_MODER6 ((uint32_t)0x00003000) |
Definition at line 6940 of file stm32f4xx.h.
| #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) |
Definition at line 6941 of file stm32f4xx.h.
| #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) |
Definition at line 6942 of file stm32f4xx.h.
| #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) |
Definition at line 6944 of file stm32f4xx.h.
| #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) |
Definition at line 6945 of file stm32f4xx.h.
| #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) |
Definition at line 6946 of file stm32f4xx.h.
| #define GPIO_MODER_MODER8 ((uint32_t)0x00030000) |
Definition at line 6948 of file stm32f4xx.h.
| #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) |
Definition at line 6949 of file stm32f4xx.h.
| #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) |
Definition at line 6950 of file stm32f4xx.h.
| #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) |
Definition at line 6952 of file stm32f4xx.h.
| #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) |
Definition at line 6953 of file stm32f4xx.h.
| #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) |
Definition at line 6954 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001) |
Definition at line 7164 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002) |
Definition at line 7165 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400) |
Definition at line 7174 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800) |
Definition at line 7175 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000) |
Definition at line 7176 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000) |
Definition at line 7177 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000) |
Definition at line 7178 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000) |
Definition at line 7179 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004) |
Definition at line 7166 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008) |
Definition at line 7167 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010) |
Definition at line 7168 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020) |
Definition at line 7169 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040) |
Definition at line 7170 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080) |
Definition at line 7171 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100) |
Definition at line 7172 of file stm32f4xx.h.
| #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200) |
Definition at line 7173 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) |
Definition at line 6999 of file stm32f4xx.h.
Referenced by GPIO_Init().
| #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) |
Definition at line 7000 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) |
Definition at line 7001 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) |
Definition at line 7003 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) |
Definition at line 7039 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) |
Definition at line 7040 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) |
Definition at line 7041 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) |
Definition at line 7043 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) |
Definition at line 7044 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) |
Definition at line 7045 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) |
Definition at line 7047 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) |
Definition at line 7048 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) |
Definition at line 7049 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) |
Definition at line 7051 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) |
Definition at line 7052 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) |
Definition at line 7053 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) |
Definition at line 7055 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) |
Definition at line 7056 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) |
Definition at line 7057 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) |
Definition at line 7059 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) |
Definition at line 7060 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) |
Definition at line 7061 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) |
Definition at line 7004 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) |
Definition at line 7005 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) |
Definition at line 7007 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) |
Definition at line 7008 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) |
Definition at line 7009 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) |
Definition at line 7011 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) |
Definition at line 7012 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) |
Definition at line 7013 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) |
Definition at line 7015 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) |
Definition at line 7016 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) |
Definition at line 7017 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) |
Definition at line 7019 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) |
Definition at line 7020 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) |
Definition at line 7021 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) |
Definition at line 7023 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) |
Definition at line 7024 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) |
Definition at line 7025 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) |
Definition at line 7027 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) |
Definition at line 7028 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) |
Definition at line 7029 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) |
Definition at line 7031 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) |
Definition at line 7032 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) |
Definition at line 7033 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) |
Definition at line 7035 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) |
Definition at line 7036 of file stm32f4xx.h.
| #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) |
Definition at line 7037 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 |
Definition at line 7146 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 |
Definition at line 7147 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 |
Definition at line 7156 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 |
Definition at line 7157 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 |
Definition at line 7158 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 |
Definition at line 7159 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 |
Definition at line 7160 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 |
Definition at line 7161 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 |
Definition at line 7148 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 |
Definition at line 7149 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 |
Definition at line 7150 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 |
Definition at line 7151 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 |
Definition at line 7152 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 |
Definition at line 7153 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 |
Definition at line 7154 of file stm32f4xx.h.
| #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 |
Definition at line 7155 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 |
Definition at line 7181 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 |
Definition at line 7182 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 |
Definition at line 7191 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 |
Definition at line 7192 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 |
Definition at line 7193 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 |
Definition at line 7194 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 |
Definition at line 7195 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 |
Definition at line 7196 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 |
Definition at line 7183 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 |
Definition at line 7184 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 |
Definition at line 7185 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 |
Definition at line 7186 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 |
Definition at line 7187 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 |
Definition at line 7188 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 |
Definition at line 7189 of file stm32f4xx.h.
| #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 |
Definition at line 7190 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) |
Definition at line 6981 of file stm32f4xx.h.
Referenced by GPIO_Init().
| #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) |
Definition at line 6982 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) |
Definition at line 6991 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) |
Definition at line 6992 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) |
Definition at line 6993 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) |
Definition at line 6994 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) |
Definition at line 6995 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) |
Definition at line 6996 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) |
Definition at line 6983 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) |
Definition at line 6984 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) |
Definition at line 6985 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) |
Definition at line 6986 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) |
Definition at line 6987 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) |
Definition at line 6988 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) |
Definition at line 6989 of file stm32f4xx.h.
| #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) |
Definition at line 6990 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) |
Definition at line 7064 of file stm32f4xx.h.
Referenced by GPIO_Init().
| #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) |
Definition at line 7065 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) |
Definition at line 7066 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) |
Definition at line 7068 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) |
Definition at line 7104 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) |
Definition at line 7105 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) |
Definition at line 7106 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) |
Definition at line 7108 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) |
Definition at line 7109 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) |
Definition at line 7110 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) |
Definition at line 7112 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) |
Definition at line 7113 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) |
Definition at line 7114 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) |
Definition at line 7116 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) |
Definition at line 7117 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) |
Definition at line 7118 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) |
Definition at line 7120 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) |
Definition at line 7121 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) |
Definition at line 7122 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) |
Definition at line 7124 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) |
Definition at line 7125 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) |
Definition at line 7126 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) |
Definition at line 7069 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) |
Definition at line 7070 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) |
Definition at line 7072 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) |
Definition at line 7073 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) |
Definition at line 7074 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) |
Definition at line 7076 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) |
Definition at line 7077 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) |
Definition at line 7078 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) |
Definition at line 7080 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) |
Definition at line 7081 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) |
Definition at line 7082 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) |
Definition at line 7084 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) |
Definition at line 7085 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) |
Definition at line 7086 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) |
Definition at line 7088 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) |
Definition at line 7089 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) |
Definition at line 7090 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) |
Definition at line 7092 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) |
Definition at line 7093 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) |
Definition at line 7094 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) |
Definition at line 7096 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) |
Definition at line 7097 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) |
Definition at line 7098 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) |
Definition at line 7100 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) |
Definition at line 7101 of file stm32f4xx.h.
| #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) |
Definition at line 7102 of file stm32f4xx.h.
| #define HASH_CR_ALGO ((uint32_t)0x00040080) |
Definition at line 7244 of file stm32f4xx.h.
Referenced by HASH_Init().
| #define HASH_CR_ALGO_0 ((uint32_t)0x00000080) |
Definition at line 7245 of file stm32f4xx.h.
| #define HASH_CR_ALGO_1 ((uint32_t)0x00040000) |
Definition at line 7246 of file stm32f4xx.h.
| #define HASH_CR_DATATYPE ((uint32_t)0x00000030) |
Definition at line 7240 of file stm32f4xx.h.
Referenced by HASH_Init().
| #define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010) |
Definition at line 7241 of file stm32f4xx.h.
| #define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020) |
Definition at line 7242 of file stm32f4xx.h.
| #define HASH_CR_DINNE ((uint32_t)0x00001000) |
Definition at line 7252 of file stm32f4xx.h.
| #define HASH_CR_DMAE ((uint32_t)0x00000008) |
Definition at line 7239 of file stm32f4xx.h.
Referenced by HASH_DMACmd().
| #define HASH_CR_INIT ((uint32_t)0x00000004) |
Definition at line 7238 of file stm32f4xx.h.
Referenced by HASH_Init(), HASH_Reset(), and HASH_RestoreContext().
| #define HASH_CR_LKEY ((uint32_t)0x00010000) |
Definition at line 7254 of file stm32f4xx.h.
| #define HASH_CR_MDMAT ((uint32_t)0x00002000) |
Definition at line 7253 of file stm32f4xx.h.
Referenced by HASH_AutoStartDigest().
| #define HASH_CR_MODE ((uint32_t)0x00000040) |
Definition at line 7243 of file stm32f4xx.h.
Referenced by HASH_Init().
| #define HASH_CR_NBW ((uint32_t)0x00000F00) |
Definition at line 7247 of file stm32f4xx.h.
Referenced by HASH_GetInFIFOWordsNbr().
| #define HASH_CR_NBW_0 ((uint32_t)0x00000100) |
Definition at line 7248 of file stm32f4xx.h.
| #define HASH_CR_NBW_1 ((uint32_t)0x00000200) |
Definition at line 7249 of file stm32f4xx.h.
| #define HASH_CR_NBW_2 ((uint32_t)0x00000400) |
Definition at line 7250 of file stm32f4xx.h.
| #define HASH_CR_NBW_3 ((uint32_t)0x00000800) |
Definition at line 7251 of file stm32f4xx.h.
| #define HASH_IMR_DCIM ((uint32_t)0x00000002) |
Definition at line 7267 of file stm32f4xx.h.
| #define HASH_IMR_DINIM ((uint32_t)0x00000001) |
Definition at line 7266 of file stm32f4xx.h.
| #define HASH_SR_BUSY ((uint32_t)0x00000008) |
Definition at line 7273 of file stm32f4xx.h.
| #define HASH_SR_DCIS ((uint32_t)0x00000002) |
Definition at line 7271 of file stm32f4xx.h.
| #define HASH_SR_DINIS ((uint32_t)0x00000001) |
Definition at line 7270 of file stm32f4xx.h.
| #define HASH_SR_DMAS ((uint32_t)0x00000004) |
Definition at line 7272 of file stm32f4xx.h.
| #define HASH_STR_DCAL ((uint32_t)0x00000100) |
Definition at line 7263 of file stm32f4xx.h.
Referenced by HASH_StartDigest().
| #define HASH_STR_NBW ((uint32_t)0x0000001F) |
Definition at line 7257 of file stm32f4xx.h.
Referenced by HASH_SetLastWordValidBitsNbr().
| #define HASH_STR_NBW_0 ((uint32_t)0x00000001) |
Definition at line 7258 of file stm32f4xx.h.
| #define HASH_STR_NBW_1 ((uint32_t)0x00000002) |
Definition at line 7259 of file stm32f4xx.h.
| #define HASH_STR_NBW_2 ((uint32_t)0x00000004) |
Definition at line 7260 of file stm32f4xx.h.
| #define HASH_STR_NBW_3 ((uint32_t)0x00000008) |
Definition at line 7261 of file stm32f4xx.h.
| #define HASH_STR_NBW_4 ((uint32_t)0x00000010) |
Definition at line 7262 of file stm32f4xx.h.
| #define I2C_CCR_CCR ((uint16_t)0x0FFF) |
Clock Control Register in Fast/Standard mode (Master mode)
Definition at line 7362 of file stm32f4xx.h.
Referenced by I2C_Init().
| #define I2C_CCR_DUTY ((uint16_t)0x4000) |
Fast Mode Duty Cycle
Definition at line 7363 of file stm32f4xx.h.
| #define I2C_CCR_FS ((uint16_t)0x8000) |
| #define I2C_CR1_ACK ((uint16_t)0x0400) |
Acknowledge Enable
Definition at line 7290 of file stm32f4xx.h.
Referenced by I2C_AcknowledgeConfig().
| #define I2C_CR1_ALERT ((uint16_t)0x2000) |
SMBus Alert
Definition at line 7293 of file stm32f4xx.h.
| #define I2C_CR1_ENARP ((uint16_t)0x0010) |
| #define I2C_CR1_ENGC ((uint16_t)0x0040) |
General Call Enable
Definition at line 7286 of file stm32f4xx.h.
Referenced by I2C_GeneralCallCmd().
| #define I2C_CR1_ENPEC ((uint16_t)0x0020) |
| #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) |
Clock Stretching Disable (Slave mode)
Definition at line 7287 of file stm32f4xx.h.
Referenced by I2C_StretchClockCmd().
| #define I2C_CR1_PE ((uint16_t)0x0001) |
Peripheral Enable
Definition at line 7281 of file stm32f4xx.h.
Referenced by I2C_Cmd(), and I2C_Init().
| #define I2C_CR1_PEC ((uint16_t)0x1000) |
| #define I2C_CR1_POS ((uint16_t)0x0800) |
Acknowledge/PEC Position (for data reception)
Definition at line 7291 of file stm32f4xx.h.
| #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) |
SMBus Type
Definition at line 7283 of file stm32f4xx.h.
| #define I2C_CR1_SMBUS ((uint16_t)0x0002) |
SMBus Mode
Definition at line 7282 of file stm32f4xx.h.
| #define I2C_CR1_START ((uint16_t)0x0100) |
| #define I2C_CR1_STOP ((uint16_t)0x0200) |
| #define I2C_CR1_SWRST ((uint16_t)0x8000) |
| #define I2C_CR2_DMAEN ((uint16_t)0x0800) |
| #define I2C_CR2_FREQ ((uint16_t)0x003F) |
FREQ[5:0] bits (Peripheral Clock Frequency)
Definition at line 7297 of file stm32f4xx.h.
Referenced by I2C_Init().
| #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) |
Bit 0
Definition at line 7298 of file stm32f4xx.h.
| #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 7299 of file stm32f4xx.h.
| #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) |
Bit 2
Definition at line 7300 of file stm32f4xx.h.
| #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) |
Bit 3
Definition at line 7301 of file stm32f4xx.h.
| #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) |
Bit 4
Definition at line 7302 of file stm32f4xx.h.
| #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) |
Bit 5
Definition at line 7303 of file stm32f4xx.h.
| #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) |
Buffer Interrupt Enable
Definition at line 7307 of file stm32f4xx.h.
| #define I2C_CR2_ITERREN ((uint16_t)0x0100) |
Error Interrupt Enable
Definition at line 7305 of file stm32f4xx.h.
| #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) |
Event Interrupt Enable
Definition at line 7306 of file stm32f4xx.h.
| #define I2C_CR2_LAST ((uint16_t)0x1000) |
DMA Last Transfer
Definition at line 7309 of file stm32f4xx.h.
Referenced by I2C_DMALastTransferCmd().
| #define I2C_DR_DR ((uint8_t)0xFF) |
8-bit Data Register
Definition at line 7333 of file stm32f4xx.h.
| #define I2C_FLTR_ANOFF ((uint8_t)0x10) |
Analog Noise Filter OFF
Definition at line 7371 of file stm32f4xx.h.
Referenced by I2C_AnalogFilterCmd().
| #define I2C_FLTR_DNF ((uint8_t)0x0F) |
Digital Noise Filter
Definition at line 7370 of file stm32f4xx.h.
Referenced by I2C_DigitalFilterConfig().
| #define I2C_OAR1_ADD0 ((uint16_t)0x0001) |
| #define I2C_OAR1_ADD1 ((uint16_t)0x0002) |
Bit 1
Definition at line 7316 of file stm32f4xx.h.
| #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) |
Interface Address
Definition at line 7312 of file stm32f4xx.h.
| #define I2C_OAR1_ADD2 ((uint16_t)0x0004) |
Bit 2
Definition at line 7317 of file stm32f4xx.h.
| #define I2C_OAR1_ADD3 ((uint16_t)0x0008) |
Bit 3
Definition at line 7318 of file stm32f4xx.h.
| #define I2C_OAR1_ADD4 ((uint16_t)0x0010) |
Bit 4
Definition at line 7319 of file stm32f4xx.h.
| #define I2C_OAR1_ADD5 ((uint16_t)0x0020) |
Bit 5
Definition at line 7320 of file stm32f4xx.h.
| #define I2C_OAR1_ADD6 ((uint16_t)0x0040) |
Bit 6
Definition at line 7321 of file stm32f4xx.h.
| #define I2C_OAR1_ADD7 ((uint16_t)0x0080) |
Bit 7
Definition at line 7322 of file stm32f4xx.h.
| #define I2C_OAR1_ADD8 ((uint16_t)0x0100) |
Bit 8
Definition at line 7323 of file stm32f4xx.h.
| #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) |
Interface Address
Definition at line 7313 of file stm32f4xx.h.
| #define I2C_OAR1_ADD9 ((uint16_t)0x0200) |
Bit 9
Definition at line 7324 of file stm32f4xx.h.
| #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) |
Addressing Mode (Slave mode)
Definition at line 7326 of file stm32f4xx.h.
| #define I2C_OAR2_ADD2 ((uint8_t)0xFE) |
Interface address
Definition at line 7330 of file stm32f4xx.h.
Referenced by I2C_OwnAddress2Config().
| #define I2C_OAR2_ENDUAL ((uint8_t)0x01) |
Dual addressing mode enable
Definition at line 7329 of file stm32f4xx.h.
Referenced by I2C_DualAddressCmd().
| #define I2C_SR1_ADD10 ((uint16_t)0x0008) |
10-bit header sent (Master mode)
Definition at line 7339 of file stm32f4xx.h.
| #define I2C_SR1_ADDR ((uint16_t)0x0002) |
Address sent (master mode)/matched (slave mode)
Definition at line 7337 of file stm32f4xx.h.
Referenced by I2C_CheckEvent().
| #define I2C_SR1_AF ((uint16_t)0x0400) |
Acknowledge Failure
Definition at line 7345 of file stm32f4xx.h.
| #define I2C_SR1_ARLO ((uint16_t)0x0200) |
Arbitration Lost (master mode)
Definition at line 7344 of file stm32f4xx.h.
| #define I2C_SR1_BERR ((uint16_t)0x0100) |
Bus Error
Definition at line 7343 of file stm32f4xx.h.
| #define I2C_SR1_BTF ((uint16_t)0x0004) |
Byte Transfer Finished
Definition at line 7338 of file stm32f4xx.h.
| #define I2C_SR1_OVR ((uint16_t)0x0800) |
Overrun/Underrun
Definition at line 7346 of file stm32f4xx.h.
| #define I2C_SR1_PECERR ((uint16_t)0x1000) |
PEC Error in reception
Definition at line 7347 of file stm32f4xx.h.
| #define I2C_SR1_RXNE ((uint16_t)0x0040) |
Data Register not Empty (receivers)
Definition at line 7341 of file stm32f4xx.h.
| #define I2C_SR1_SB ((uint16_t)0x0001) |
Start Bit (Master mode)
Definition at line 7336 of file stm32f4xx.h.
| #define I2C_SR1_SMBALERT ((uint16_t)0x8000) |
SMBus Alert
Definition at line 7349 of file stm32f4xx.h.
| #define I2C_SR1_STOPF ((uint16_t)0x0010) |
Stop detection (Slave mode)
Definition at line 7340 of file stm32f4xx.h.
Referenced by I2C_CheckEvent().
| #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) |
Timeout or Tlow Error
Definition at line 7348 of file stm32f4xx.h.
| #define I2C_SR1_TXE ((uint16_t)0x0080) |
Data Register Empty (transmitters)
Definition at line 7342 of file stm32f4xx.h.
| #define I2C_SR2_BUSY ((uint16_t)0x0002) |
Bus Busy
Definition at line 7353 of file stm32f4xx.h.
| #define I2C_SR2_DUALF ((uint16_t)0x0080) |
Dual Flag (Slave mode)
Definition at line 7358 of file stm32f4xx.h.
| #define I2C_SR2_GENCALL ((uint16_t)0x0010) |
General Call Address (Slave mode)
Definition at line 7355 of file stm32f4xx.h.
| #define I2C_SR2_MSL ((uint16_t)0x0001) |
Master/Slave
Definition at line 7352 of file stm32f4xx.h.
| #define I2C_SR2_PEC ((uint16_t)0xFF00) |
Packet Error Checking Register
Definition at line 7359 of file stm32f4xx.h.
| #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) |
SMBus Device Default Address (Slave mode)
Definition at line 7356 of file stm32f4xx.h.
| #define I2C_SR2_SMBHOST ((uint16_t)0x0040) |
SMBus Host Header (Slave mode)
Definition at line 7357 of file stm32f4xx.h.
| #define I2C_SR2_TRA ((uint16_t)0x0004) |
Transmitter/Receiver
Definition at line 7354 of file stm32f4xx.h.
| #define I2C_TRISE_TRISE ((uint8_t)0x3F) |
Maximum Rise Time in Fast/Standard mode (Master mode)
Definition at line 7367 of file stm32f4xx.h.
| #define IWDG_KR_KEY ((uint16_t)0xFFFF) |
Key value (write only, read 0000h)
Definition at line 7482 of file stm32f4xx.h.
| #define IWDG_PR_PR ((uint8_t)0x07) |
PR[2:0] (Prescaler divider)
Definition at line 7485 of file stm32f4xx.h.
| #define IWDG_PR_PR_0 ((uint8_t)0x01) |
Bit 0
Definition at line 7486 of file stm32f4xx.h.
| #define IWDG_PR_PR_1 ((uint8_t)0x02) |
Bit 1
Definition at line 7487 of file stm32f4xx.h.
| #define IWDG_PR_PR_2 ((uint8_t)0x04) |
Bit 2
Definition at line 7488 of file stm32f4xx.h.
| #define IWDG_RLR_RL ((uint16_t)0x0FFF) |
Watchdog counter reload value
Definition at line 7491 of file stm32f4xx.h.
| #define IWDG_SR_PVU ((uint8_t)0x01) |
Watchdog prescaler value update
Definition at line 7494 of file stm32f4xx.h.
| #define IWDG_SR_RVU ((uint8_t)0x02) |
Watchdog counter reload value update
Definition at line 7495 of file stm32f4xx.h.
| #define LTDC_AWCR_AAH ((uint32_t)0x000007FF) |
| #define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) |
| #define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) |
| #define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) |
| #define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) |
| #define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) |
Accumulated Horizontal Back Porch
Definition at line 7511 of file stm32f4xx.h.
Referenced by LTDC_Init().
| #define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) |
Accumulated Vertical Back Porch
Definition at line 7510 of file stm32f4xx.h.
Referenced by LTDC_Init().
| #define LTDC_CDSR_HDES ((uint32_t)0x00000002) |
Horizontal Data Enable Status
Definition at line 7582 of file stm32f4xx.h.
| #define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) |
Horizontal Synchronization Status
Definition at line 7584 of file stm32f4xx.h.
| #define LTDC_CDSR_VDES ((uint32_t)0x00000001) |
Vertical Data Enable Status
Definition at line 7581 of file stm32f4xx.h.
| #define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) |
Vertical Synchronization Status
Definition at line 7583 of file stm32f4xx.h.
| #define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) |
| #define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) |
| #define LTDC_GCR_DBW ((uint32_t)0x00000070) |
Dither Blue Width
Definition at line 7526 of file stm32f4xx.h.
| #define LTDC_GCR_DEN ((uint32_t)0x00010000) |
Dither Enable
Definition at line 7529 of file stm32f4xx.h.
| #define LTDC_GCR_DEPOL ((uint32_t)0x20000000) |
Data Enable Polarity
Definition at line 7531 of file stm32f4xx.h.
| #define LTDC_GCR_DGW ((uint32_t)0x00000700) |
Dither Green Width
Definition at line 7527 of file stm32f4xx.h.
| #define LTDC_GCR_DRW ((uint32_t)0x00007000) |
Dither Red Width
Definition at line 7528 of file stm32f4xx.h.
| #define LTDC_GCR_DTEN LTDC_GCR_DEN |
Definition at line 7536 of file stm32f4xx.h.
Referenced by LTDC_DitherCmd().
| #define LTDC_GCR_HSPOL ((uint32_t)0x80000000) |
Horizontal Synchronization Polarity
Definition at line 7533 of file stm32f4xx.h.
| #define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) |
LCD-TFT controller enable bit
Definition at line 7525 of file stm32f4xx.h.
Referenced by LTDC_Cmd().
| #define LTDC_GCR_PCPOL ((uint32_t)0x10000000) |
Pixel Clock Polarity
Definition at line 7530 of file stm32f4xx.h.
| #define LTDC_GCR_VSPOL ((uint32_t)0x40000000) |
Vertical Synchronization Polarity
Definition at line 7532 of file stm32f4xx.h.
| #define LTDC_ICR_CFUIF ((uint32_t)0x00000002) |
Clears the FIFO Underrun Interrupt Flag
Definition at line 7566 of file stm32f4xx.h.
| #define LTDC_ICR_CLIF ((uint32_t)0x00000001) |
Clears the Line Interrupt Flag
Definition at line 7565 of file stm32f4xx.h.
| #define LTDC_ICR_CRRIF ((uint32_t)0x00000008) |
Clears Register Reload interrupt Flag
Definition at line 7568 of file stm32f4xx.h.
| #define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) |
Clears the Transfer Error Interrupt Flag
Definition at line 7567 of file stm32f4xx.h.
| #define LTDC_IER_FUIE ((uint32_t)0x00000002) |
FIFO Underrun Interrupt Enable
Definition at line 7552 of file stm32f4xx.h.
| #define LTDC_IER_LIE ((uint32_t)0x00000001) |
Line Interrupt Enable
Definition at line 7551 of file stm32f4xx.h.
| #define LTDC_IER_RRIE ((uint32_t)0x00000008) |
Register Reload interrupt enable
Definition at line 7554 of file stm32f4xx.h.
| #define LTDC_IER_TERRIE ((uint32_t)0x00000004) |
Transfer Error Interrupt Enable
Definition at line 7553 of file stm32f4xx.h.
| #define LTDC_ISR_FUIF ((uint32_t)0x00000002) |
FIFO Underrun Interrupt Flag
Definition at line 7559 of file stm32f4xx.h.
| #define LTDC_ISR_LIF ((uint32_t)0x00000001) |
Line Interrupt Flag
Definition at line 7558 of file stm32f4xx.h.
| #define LTDC_ISR_RRIF ((uint32_t)0x00000008) |
Register Reload interrupt Flag
Definition at line 7561 of file stm32f4xx.h.
| #define LTDC_ISR_TERRIF ((uint32_t)0x00000004) |
Transfer Error Interrupt Flag
Definition at line 7560 of file stm32f4xx.h.
| #define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) |
Line Interrupt Position
Definition at line 7572 of file stm32f4xx.h.
| #define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) |
| #define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) |
| #define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) |
| #define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) |
Color Frame Buffer Start Address
Definition at line 7630 of file stm32f4xx.h.
Referenced by LTDC_LayerInit().
| #define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) |
Frame Buffer Line Number
Definition at line 7639 of file stm32f4xx.h.
Referenced by LTDC_LayerInit().
| #define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) |
Color Frame Buffer Line Length
Definition at line 7634 of file stm32f4xx.h.
Referenced by LTDC_LayerInit().
| #define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) |
Color Frame Buffer Pitch in bytes
Definition at line 7635 of file stm32f4xx.h.
Referenced by LTDC_LayerInit().
| #define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) |
Color Key Blue value
Definition at line 7604 of file stm32f4xx.h.
Referenced by LTDC_ColorKeyingConfig().
| #define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) |
Color Key Green value
Definition at line 7605 of file stm32f4xx.h.
Referenced by LTDC_ColorKeyingConfig().
| #define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) |
Color Key Red value
Definition at line 7606 of file stm32f4xx.h.
Referenced by LTDC_ColorKeyingConfig().
| #define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) |
Blue value
Definition at line 7643 of file stm32f4xx.h.
| #define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) |
CLUT address
Definition at line 7646 of file stm32f4xx.h.
| #define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) |
Green value
Definition at line 7644 of file stm32f4xx.h.
| #define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) |
Red value
Definition at line 7645 of file stm32f4xx.h.
| #define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) |
Color Lockup Table Enable
Definition at line 7590 of file stm32f4xx.h.
Referenced by LTDC_CLUTCmd().
| #define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) |
Color Keying Enable
Definition at line 7589 of file stm32f4xx.h.
Referenced by LTDC_ColorKeyingConfig().
| #define LTDC_LxCR_LEN ((uint32_t)0x00000001) |
| #define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) |
| #define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) |
| #define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) |
| #define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) |
| #define LTDC_LxPFCR_PF ((uint32_t)0x00000007) |
| #define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) |
Window Horizontal Stop Position
Definition at line 7595 of file stm32f4xx.h.
Referenced by LTDC_LayerInit(), and LTDC_LayerPosition().
| #define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) |
Window Horizontal Start Position
Definition at line 7594 of file stm32f4xx.h.
Referenced by LTDC_LayerInit(), and LTDC_LayerPosition().
| #define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) |
Window Vertical Stop Position
Definition at line 7600 of file stm32f4xx.h.
Referenced by LTDC_LayerInit(), and LTDC_LayerPosition().
| #define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) |
Window Vertical Start Position
Definition at line 7599 of file stm32f4xx.h.
Referenced by LTDC_LayerInit(), and LTDC_LayerPosition().
| #define LTDC_SRCR_IMR ((uint32_t)0x00000001) |
Immediate Reload
Definition at line 7540 of file stm32f4xx.h.
| #define LTDC_SRCR_VBR ((uint32_t)0x00000002) |
Vertical Blanking Reload
Definition at line 7541 of file stm32f4xx.h.
| #define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) |
Horizontal Synchronization Width
Definition at line 7506 of file stm32f4xx.h.
Referenced by LTDC_Init().
| #define LTDC_SSCR_VSH ((uint32_t)0x000007FF) |
Vertical Synchronization Height
Definition at line 7505 of file stm32f4xx.h.
Referenced by LTDC_Init().
| #define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) |
| #define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) |
| #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) |
Refer to AN4073 on how to use this bit
Definition at line 8874 of file stm32f4xx.h.
| #define PWR_CR_CSBF ((uint32_t)0x00000008) |
Clear Standby Flag
Definition at line 8848 of file stm32f4xx.h.
| #define PWR_CR_CWUF ((uint32_t)0x00000004) |
Clear Wakeup Flag
Definition at line 8847 of file stm32f4xx.h.
| #define PWR_CR_DBP ((uint32_t)0x00000100) |
Disable Backup Domain write protection
Definition at line 8866 of file stm32f4xx.h.
| #define PWR_CR_FISSR ((uint32_t)0x00200000) |
Flash Interface Stop while System Run
Definition at line 8887 of file stm32f4xx.h.
Referenced by FLASH_FlashInterfaceCmd().
| #define PWR_CR_FMSSR ((uint32_t)0x00100000) |
Flash Memory Sleep System Run
Definition at line 8886 of file stm32f4xx.h.
Referenced by FLASH_FlashSleepModeCmd().
| #define PWR_CR_FPDS ((uint32_t)0x00000200) |
Flash power down in Stop mode
Definition at line 8867 of file stm32f4xx.h.
| #define PWR_CR_LPDS ((uint32_t)0x00000001) |
Low-Power Deepsleep
Definition at line 8845 of file stm32f4xx.h.
| #define PWR_CR_LPLVDS ((uint32_t)0x00000400) |
Low-power regulator Low Voltage in Deep Sleep mode
Definition at line 8871 of file stm32f4xx.h.
| #define PWR_CR_LPUDS ((uint32_t)0x00000400) |
Low-Power Regulator in Stop under-drive mode
Definition at line 8868 of file stm32f4xx.h.
| #define PWR_CR_MRLVDS ((uint32_t)0x00000800) |
Main regulator Low Voltage in Deep Sleep mode
Definition at line 8872 of file stm32f4xx.h.
| #define PWR_CR_MRUDS ((uint32_t)0x00000800) |
Main regulator in Stop under-drive mode
Definition at line 8869 of file stm32f4xx.h.
| #define PWR_CR_ODEN ((uint32_t)0x00010000) |
| #define PWR_CR_ODSWEN ((uint32_t)0x00020000) |
| #define PWR_CR_PDDS ((uint32_t)0x00000002) |
Power Down Deepsleep
Definition at line 8846 of file stm32f4xx.h.
Referenced by PWR_EnterSTANDBYMode().
| #define PWR_CR_PLS ((uint32_t)0x000000E0) |
PLS[2:0] bits (PVD Level Selection)
Definition at line 8851 of file stm32f4xx.h.
| #define PWR_CR_PLS_0 ((uint32_t)0x00000020) |
Bit 0
Definition at line 8852 of file stm32f4xx.h.
| #define PWR_CR_PLS_1 ((uint32_t)0x00000040) |
Bit 1
Definition at line 8853 of file stm32f4xx.h.
| #define PWR_CR_PLS_2 ((uint32_t)0x00000080) |
Bit 2 PVD level configuration
Definition at line 8854 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) |
PVD level 0
Definition at line 8857 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) |
PVD level 1
Definition at line 8858 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) |
PVD level 2
Definition at line 8859 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) |
PVD level 3
Definition at line 8860 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) |
PVD level 4
Definition at line 8861 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) |
PVD level 5
Definition at line 8862 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) |
PVD level 6
Definition at line 8863 of file stm32f4xx.h.
| #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) |
PVD level 7
Definition at line 8864 of file stm32f4xx.h.
| #define PWR_CR_PMODE PWR_CR_VOS |
Definition at line 8890 of file stm32f4xx.h.
| #define PWR_CR_PVDE ((uint32_t)0x00000010) |
Power Voltage Detector Enable
Definition at line 8849 of file stm32f4xx.h.
| #define PWR_CR_UDEN ((uint32_t)0x000C0000) |
Under Drive enable in stop mode
Definition at line 8882 of file stm32f4xx.h.
Referenced by PWR_UnderDriveCmd().
| #define PWR_CR_UDEN_0 ((uint32_t)0x00040000) |
Bit 0
Definition at line 8883 of file stm32f4xx.h.
| #define PWR_CR_UDEN_1 ((uint32_t)0x00080000) |
Bit 1
Definition at line 8884 of file stm32f4xx.h.
| #define PWR_CR_VOS ((uint32_t)0x0000C000) |
VOS[1:0] bits (Regulator voltage scaling output selection)
Definition at line 8876 of file stm32f4xx.h.
Referenced by SetSysClock().
| #define PWR_CR_VOS_0 ((uint32_t)0x00004000) |
Bit 0
Definition at line 8877 of file stm32f4xx.h.
| #define PWR_CR_VOS_1 ((uint32_t)0x00008000) |
Bit 1
Definition at line 8878 of file stm32f4xx.h.
| #define PWR_CSR_BRE ((uint32_t)0x00000200) |
Backup regulator enable
Definition at line 8899 of file stm32f4xx.h.
| #define PWR_CSR_BRR ((uint32_t)0x00000008) |
Backup regulator ready
Definition at line 8896 of file stm32f4xx.h.
| #define PWR_CSR_EWUP ((uint32_t)0x00000100) |
Enable WKUP pin
Definition at line 8898 of file stm32f4xx.h.
| #define PWR_CSR_ODRDY ((uint32_t)0x00010000) |
Over Drive generator ready
Definition at line 8901 of file stm32f4xx.h.
Referenced by SetSysClock().
| #define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) |
| #define PWR_CSR_PVDO ((uint32_t)0x00000004) |
PVD Output
Definition at line 8895 of file stm32f4xx.h.
| #define PWR_CSR_REGRDY PWR_CSR_VOSRDY |
Definition at line 8906 of file stm32f4xx.h.
| #define PWR_CSR_SBF ((uint32_t)0x00000002) |
Standby Flag
Definition at line 8894 of file stm32f4xx.h.
| #define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) |
Under Drive ready
Definition at line 8903 of file stm32f4xx.h.
| #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) |
Regulator voltage scaling output selection ready
Definition at line 8900 of file stm32f4xx.h.
| #define PWR_CSR_WUF ((uint32_t)0x00000001) |
Wakeup Flag
Definition at line 8893 of file stm32f4xx.h.
| #define PWR_CSR_WUPP ((uint32_t)0x00000080) |
WKUP pin Polarity
Definition at line 8897 of file stm32f4xx.h.
| #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000) |
Definition at line 9376 of file stm32f4xx.h.
| #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000) |
Definition at line 9377 of file stm32f4xx.h.
| #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000) |
Definition at line 9375 of file stm32f4xx.h.
| #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000) |
Definition at line 9378 of file stm32f4xx.h.
| #define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000) |
Definition at line 9380 of file stm32f4xx.h.
| #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000) |
Definition at line 9379 of file stm32f4xx.h.
| #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000) |
Definition at line 9381 of file stm32f4xx.h.
| #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000) |
Definition at line 9384 of file stm32f4xx.h.
| #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000) |
Definition at line 9383 of file stm32f4xx.h.
| #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000) |
Definition at line 9382 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001) |
Definition at line 9364 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002) |
Definition at line 9365 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004) |
Definition at line 9366 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008) |
Definition at line 9367 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010) |
Definition at line 9368 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020) |
Definition at line 9369 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040) |
Definition at line 9370 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080) |
Definition at line 9371 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100) |
Definition at line 9372 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200) |
Definition at line 9373 of file stm32f4xx.h.
| #define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400) |
Definition at line 9374 of file stm32f4xx.h.
| #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000) |
Definition at line 9385 of file stm32f4xx.h.
| #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000) |
Definition at line 9386 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000) |
Definition at line 9498 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000) |
Definition at line 9494 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000) |
Definition at line 9500 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000) |
Definition at line 9502 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000) |
Definition at line 9501 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000) |
Definition at line 9503 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000) |
Definition at line 9506 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000) |
Definition at line 9505 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000) |
Definition at line 9504 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000) |
Definition at line 9495 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001) |
Definition at line 9483 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002) |
Definition at line 9484 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004) |
Definition at line 9485 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008) |
Definition at line 9486 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010) |
Definition at line 9487 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020) |
Definition at line 9488 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040) |
Definition at line 9489 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080) |
Definition at line 9490 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100) |
Definition at line 9491 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200) |
Definition at line 9492 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400) |
Definition at line 9493 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000) |
Definition at line 9507 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000) |
Definition at line 9508 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000) |
Definition at line 9496 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000) |
Definition at line 9497 of file stm32f4xx.h.
| #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000) |
Definition at line 9499 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000) |
Definition at line 9260 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000) |
Definition at line 9261 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000) |
Definition at line 9263 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) |
Definition at line 9262 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) |
Definition at line 9264 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001) |
Definition at line 9249 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002) |
Definition at line 9250 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004) |
Definition at line 9251 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008) |
Definition at line 9252 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010) |
Definition at line 9253 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020) |
Definition at line 9254 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040) |
Definition at line 9255 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080) |
Definition at line 9256 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100) |
Definition at line 9257 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200) |
Definition at line 9258 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400) |
Definition at line 9259 of file stm32f4xx.h.
| #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000) |
Definition at line 9265 of file stm32f4xx.h.
| #define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010) |
Definition at line 9390 of file stm32f4xx.h.
| #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001) |
Definition at line 9389 of file stm32f4xx.h.
| #define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020) |
Definition at line 9391 of file stm32f4xx.h.
| #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080) |
Definition at line 9393 of file stm32f4xx.h.
| #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040) |
Definition at line 9392 of file stm32f4xx.h.
| #define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010) |
Definition at line 9512 of file stm32f4xx.h.
| #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001) |
Definition at line 9511 of file stm32f4xx.h.
| #define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020) |
Definition at line 9513 of file stm32f4xx.h.
| #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080) |
Definition at line 9515 of file stm32f4xx.h.
| #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040) |
Definition at line 9514 of file stm32f4xx.h.
| #define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010) |
Definition at line 9269 of file stm32f4xx.h.
| #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) |
Definition at line 9268 of file stm32f4xx.h.
| #define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020) |
Definition at line 9270 of file stm32f4xx.h.
| #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST |
Definition at line 9272 of file stm32f4xx.h.
| #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080) |
Definition at line 9274 of file stm32f4xx.h.
| #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) |
Definition at line 9273 of file stm32f4xx.h.
| #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
Definition at line 9438 of file stm32f4xx.h.
| #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) |
Definition at line 9439 of file stm32f4xx.h.
| #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
Definition at line 9444 of file stm32f4xx.h.
| #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
Definition at line 9432 of file stm32f4xx.h.
| #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
Definition at line 9433 of file stm32f4xx.h.
| #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000) |
Definition at line 9434 of file stm32f4xx.h.
| #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
Definition at line 9443 of file stm32f4xx.h.
Referenced by SetSysClock().
| #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
Definition at line 9423 of file stm32f4xx.h.
| #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
Definition at line 9424 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) |
Definition at line 9416 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) |
Definition at line 9417 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) |
Definition at line 9418 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
Definition at line 9410 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
Definition at line 9411 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
Definition at line 9412 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
Definition at line 9413 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
Definition at line 9414 of file stm32f4xx.h.
| #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
Definition at line 9415 of file stm32f4xx.h.
| #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
Definition at line 9430 of file stm32f4xx.h.
| #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
Definition at line 9431 of file stm32f4xx.h.
| #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000) |
Definition at line 9445 of file stm32f4xx.h.
| #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000) |
Definition at line 9446 of file stm32f4xx.h.
| #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
Definition at line 9428 of file stm32f4xx.h.
| #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
Definition at line 9429 of file stm32f4xx.h.
| #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
Definition at line 9422 of file stm32f4xx.h.
| #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000) |
Definition at line 9558 of file stm32f4xx.h.
| #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000) |
Definition at line 9559 of file stm32f4xx.h.
| #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) |
Definition at line 9564 of file stm32f4xx.h.
| #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) |
Definition at line 9552 of file stm32f4xx.h.
| #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) |
Definition at line 9553 of file stm32f4xx.h.
| #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000) |
Definition at line 9554 of file stm32f4xx.h.
| #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) |
Definition at line 9563 of file stm32f4xx.h.
| #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) |
Definition at line 9543 of file stm32f4xx.h.
| #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) |
Definition at line 9544 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040) |
Definition at line 9536 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080) |
Definition at line 9537 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100) |
Definition at line 9538 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) |
Definition at line 9530 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) |
Definition at line 9531 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) |
Definition at line 9532 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) |
Definition at line 9533 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) |
Definition at line 9534 of file stm32f4xx.h.
| #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) |
Definition at line 9535 of file stm32f4xx.h.
| #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) |
Definition at line 9550 of file stm32f4xx.h.
| #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) |
Definition at line 9551 of file stm32f4xx.h.
| #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000) |
Definition at line 9565 of file stm32f4xx.h.
| #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000) |
Definition at line 9566 of file stm32f4xx.h.
| #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) |
Definition at line 9548 of file stm32f4xx.h.
| #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) |
Definition at line 9549 of file stm32f4xx.h.
| #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) |
Definition at line 9542 of file stm32f4xx.h.
| #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
Definition at line 9317 of file stm32f4xx.h.
| #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) |
Definition at line 9318 of file stm32f4xx.h.
| #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
Definition at line 9323 of file stm32f4xx.h.
| #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
Definition at line 9311 of file stm32f4xx.h.
| #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
Definition at line 9312 of file stm32f4xx.h.
| #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000) |
Definition at line 9313 of file stm32f4xx.h.
| #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
Definition at line 9322 of file stm32f4xx.h.
| #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
Definition at line 9302 of file stm32f4xx.h.
| #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) |
Definition at line 9303 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) |
Definition at line 9295 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) |
Definition at line 9296 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) |
Definition at line 9297 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
Definition at line 9289 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
Definition at line 9290 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
Definition at line 9291 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
Definition at line 9292 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
Definition at line 9293 of file stm32f4xx.h.
| #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
Definition at line 9294 of file stm32f4xx.h.
| #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
Definition at line 9309 of file stm32f4xx.h.
| #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
Definition at line 9310 of file stm32f4xx.h.
| #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000) |
Definition at line 9324 of file stm32f4xx.h.
| #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000) |
Definition at line 9325 of file stm32f4xx.h.
| #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
Definition at line 9307 of file stm32f4xx.h.
| #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
Definition at line 9308 of file stm32f4xx.h.
| #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
Definition at line 9301 of file stm32f4xx.h.
| #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100) |
Definition at line 9455 of file stm32f4xx.h.
| #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200) |
Definition at line 9456 of file stm32f4xx.h.
| #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400) |
Definition at line 9457 of file stm32f4xx.h.
| #define RCC_APB2ENR_EXTIEN ((uint32_t)0x00008000) |
Definition at line 9462 of file stm32f4xx.h.
| #define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000) |
Definition at line 9472 of file stm32f4xx.h.
| #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000) |
Definition at line 9468 of file stm32f4xx.h.
| #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) |
Definition at line 9458 of file stm32f4xx.h.
| #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
Definition at line 9459 of file stm32f4xx.h.
| #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000) |
Definition at line 9460 of file stm32f4xx.h.
| #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000) |
Definition at line 9466 of file stm32f4xx.h.
| #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000) |
Definition at line 9467 of file stm32f4xx.h.
| #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000) |
Definition at line 9461 of file stm32f4xx.h.
| #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000) |
Definition at line 9464 of file stm32f4xx.h.
| #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000) |
Definition at line 9465 of file stm32f4xx.h.
| #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001) |
Definition at line 9449 of file stm32f4xx.h.
| #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002) |
Definition at line 9450 of file stm32f4xx.h.
| #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000) |
Definition at line 9463 of file stm32f4xx.h.
| #define RCC_APB2ENR_UART10EN ((uint32_t)0x00000080) |
Definition at line 9454 of file stm32f4xx.h.
| #define RCC_APB2ENR_UART9EN ((uint32_t)0x00000040) |
Definition at line 9453 of file stm32f4xx.h.
| #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010) |
Definition at line 9451 of file stm32f4xx.h.
| #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) |
Definition at line 9452 of file stm32f4xx.h.
| #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100) |
Definition at line 9575 of file stm32f4xx.h.
| #define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200) |
Definition at line 9576 of file stm32f4xx.h.
| #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400) |
Definition at line 9577 of file stm32f4xx.h.
| #define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000) |
Definition at line 9591 of file stm32f4xx.h.
| #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000) |
Definition at line 9587 of file stm32f4xx.h.
| #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) |
Definition at line 9578 of file stm32f4xx.h.
| #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) |
Definition at line 9579 of file stm32f4xx.h.
| #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000) |
Definition at line 9580 of file stm32f4xx.h.
| #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000) |
Definition at line 9585 of file stm32f4xx.h.
| #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000) |
Definition at line 9586 of file stm32f4xx.h.
| #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000) |
Definition at line 9581 of file stm32f4xx.h.
| #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000) |
Definition at line 9583 of file stm32f4xx.h.
| #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000) |
Definition at line 9584 of file stm32f4xx.h.
| #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001) |
Definition at line 9569 of file stm32f4xx.h.
| #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002) |
Definition at line 9570 of file stm32f4xx.h.
| #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000) |
Definition at line 9582 of file stm32f4xx.h.
| #define RCC_APB2LPENR_UART10LPEN ((uint32_t)0x00000080) |
Definition at line 9574 of file stm32f4xx.h.
| #define RCC_APB2LPENR_UART9LPEN ((uint32_t)0x00000040) |
Definition at line 9573 of file stm32f4xx.h.
| #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010) |
Definition at line 9571 of file stm32f4xx.h.
| #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020) |
Definition at line 9572 of file stm32f4xx.h.
| #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100) |
Definition at line 9334 of file stm32f4xx.h.
| #define RCC_APB2RSTR_DFSDMRST RCC_APB2RSTR_DFSDM1RST |
Definition at line 9361 of file stm32f4xx.h.
| #define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000) |
Definition at line 9348 of file stm32f4xx.h.
| #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000) |
Definition at line 9344 of file stm32f4xx.h.
| #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) |
Definition at line 9335 of file stm32f4xx.h.
| #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST |
Definition at line 9360 of file stm32f4xx.h.
| #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
Definition at line 9336 of file stm32f4xx.h.
| #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000) |
Definition at line 9337 of file stm32f4xx.h.
| #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000) |
Definition at line 9342 of file stm32f4xx.h.
| #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000) |
Definition at line 9343 of file stm32f4xx.h.
| #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000) |
Definition at line 9338 of file stm32f4xx.h.
| #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000) |
Definition at line 9340 of file stm32f4xx.h.
| #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000) |
Definition at line 9341 of file stm32f4xx.h.
| #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001) |
Definition at line 9328 of file stm32f4xx.h.
| #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002) |
Definition at line 9329 of file stm32f4xx.h.
| #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000) |
Definition at line 9339 of file stm32f4xx.h.
| #define RCC_APB2RSTR_UART10RST ((uint32_t)0x00000080) |
Definition at line 9333 of file stm32f4xx.h.
| #define RCC_APB2RSTR_UART9RST ((uint32_t)0x00000040) |
Definition at line 9332 of file stm32f4xx.h.
| #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010) |
Definition at line 9330 of file stm32f4xx.h.
| #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) |
Definition at line 9331 of file stm32f4xx.h.
| #define RCC_BDCR_BDRST ((uint32_t)0x00010000) |
Definition at line 9613 of file stm32f4xx.h.
| #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
Definition at line 9605 of file stm32f4xx.h.
| #define RCC_BDCR_LSEMOD ((uint32_t)0x00000008) |
Definition at line 9606 of file stm32f4xx.h.
Referenced by RCC_LSEModeConfig().
| #define RCC_BDCR_LSEON ((uint32_t)0x00000001) |
Definition at line 9603 of file stm32f4xx.h.
| #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
Definition at line 9604 of file stm32f4xx.h.
| #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
Definition at line 9612 of file stm32f4xx.h.
| #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
Definition at line 9608 of file stm32f4xx.h.
| #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
Definition at line 9609 of file stm32f4xx.h.
| #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
Definition at line 9610 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
< HPRE configuration HPRE[3:0] bits (AHB prescaler)
Definition at line 9148 of file stm32f4xx.h.
Referenced by RCC_GetClocksFreq(), and SystemCoreClockUpdate().
| #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 9149 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 9150 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
Bit 2
Definition at line 9151 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
Bit 3
Definition at line 9152 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
SYSCLK divided by 128
Definition at line 9160 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
SYSCLK divided by 16
Definition at line 9158 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
SYSCLK divided by 2
Definition at line 9155 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
SYSCLK divided by 256
Definition at line 9161 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
SYSCLK divided by 4
Definition at line 9156 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
SYSCLK divided by 512
Definition at line 9162 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
SYSCLK divided by 64
Definition at line 9159 of file stm32f4xx.h.
| #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
SYSCLK divided by 8
Definition at line 9157 of file stm32f4xx.h.
| #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) |
Definition at line 9207 of file stm32f4xx.h.
Referenced by I2S_Init().
| #define RCC_CFGR_MCO1 ((uint32_t)0x00600000) |
Definition at line 9203 of file stm32f4xx.h.
| #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000) |
Definition at line 9204 of file stm32f4xx.h.
| #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000) |
Definition at line 9205 of file stm32f4xx.h.
| #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000) |
Definition at line 9209 of file stm32f4xx.h.
| #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000) |
Definition at line 9210 of file stm32f4xx.h.
| #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000) |
Definition at line 9211 of file stm32f4xx.h.
| #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000) |
Definition at line 9212 of file stm32f4xx.h.
| #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000) |
Definition at line 9219 of file stm32f4xx.h.
| #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000) |
Definition at line 9220 of file stm32f4xx.h.
| #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000) |
Definition at line 9221 of file stm32f4xx.h.
| #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000) |
Definition at line 9214 of file stm32f4xx.h.
| #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000) |
Definition at line 9215 of file stm32f4xx.h.
| #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000) |
Definition at line 9216 of file stm32f4xx.h.
| #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000) |
Definition at line 9217 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) |
< PPRE1 configuration PRE1[2:0] bits (APB1 prescaler)
Definition at line 9171 of file stm32f4xx.h.
Referenced by RCC_GetClocksFreq().
| #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) |
Bit 0
Definition at line 9172 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) |
Bit 1
Definition at line 9173 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) |
Bit 2
Definition at line 9174 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
HCLK not divided
Definition at line 9176 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) |
HCLK divided by 16 PPRE2 configuration
Definition at line 9180 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) |
| #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) |
| #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) |
HCLK divided by 8
Definition at line 9179 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) |
PRE2[2:0] bits (APB2 prescaler)
Definition at line 9183 of file stm32f4xx.h.
Referenced by RCC_GetClocksFreq().
| #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) |
Bit 0
Definition at line 9184 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) |
Bit 1
Definition at line 9185 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) |
Bit 2
Definition at line 9186 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) |
HCLK divided by 16 RTCPRE configuration
Definition at line 9192 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) |
| #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) |
HCLK divided by 4
Definition at line 9190 of file stm32f4xx.h.
| #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) |
HCLK divided by 8
Definition at line 9191 of file stm32f4xx.h.
| #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000) |
Definition at line 9195 of file stm32f4xx.h.
| #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000) |
Definition at line 9196 of file stm32f4xx.h.
| #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000) |
Definition at line 9197 of file stm32f4xx.h.
| #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000) |
Definition at line 9198 of file stm32f4xx.h.
| #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000) |
Definition at line 9199 of file stm32f4xx.h.
| #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000) |
MCO1 configuration
Definition at line 9200 of file stm32f4xx.h.
| #define RCC_CFGR_SW ((uint32_t)0x00000003) |
< SW configuration SW[1:0] bits (System clock Switch)
Definition at line 9124 of file stm32f4xx.h.
Referenced by SetSysClock().
| #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 9125 of file stm32f4xx.h.
| #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 9126 of file stm32f4xx.h.
| #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
HSE selected as system clock
Definition at line 9129 of file stm32f4xx.h.
| #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
HSI selected as system clock
Definition at line 9128 of file stm32f4xx.h.
| #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
PLL/PLLP selected as system clock
Definition at line 9130 of file stm32f4xx.h.
Referenced by SetSysClock().
| #define RCC_CFGR_SWS ((uint32_t)0x0000000C) |
< SWS configuration SWS[1:0] bits (System Clock Switch Status)
Definition at line 9136 of file stm32f4xx.h.
Referenced by RCC_GetClocksFreq(), RCC_GetSYSCLKSource(), SetSysClock(), and SystemCoreClockUpdate().
| #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
Bit 0
Definition at line 9137 of file stm32f4xx.h.
| #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
Bit 1
Definition at line 9138 of file stm32f4xx.h.
| #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
HSE oscillator used as system clock
Definition at line 9141 of file stm32f4xx.h.
| #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
HSI oscillator used as system clock
Definition at line 9140 of file stm32f4xx.h.
| #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
PLL/PLLP used as system clock
Definition at line 9142 of file stm32f4xx.h.
Referenced by SetSysClock().
| #define RCC_CIR_CSSC ((uint32_t)0x00800000) |
Definition at line 9246 of file stm32f4xx.h.
| #define RCC_CIR_CSSF ((uint32_t)0x00000080) |
Definition at line 9231 of file stm32f4xx.h.
| #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
Definition at line 9242 of file stm32f4xx.h.
| #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
Definition at line 9227 of file stm32f4xx.h.
| #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
Definition at line 9235 of file stm32f4xx.h.
| #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
Definition at line 9241 of file stm32f4xx.h.
| #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
Definition at line 9226 of file stm32f4xx.h.
| #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
Definition at line 9234 of file stm32f4xx.h.
| #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
Definition at line 9240 of file stm32f4xx.h.
| #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
Definition at line 9225 of file stm32f4xx.h.
| #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
Definition at line 9233 of file stm32f4xx.h.
| #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
Definition at line 9239 of file stm32f4xx.h.
| #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
Definition at line 9224 of file stm32f4xx.h.
| #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
Definition at line 9232 of file stm32f4xx.h.
| #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000) |
Definition at line 9244 of file stm32f4xx.h.
| #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020) |
Definition at line 9229 of file stm32f4xx.h.
| #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000) |
Definition at line 9237 of file stm32f4xx.h.
| #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
Definition at line 9243 of file stm32f4xx.h.
| #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
Definition at line 9228 of file stm32f4xx.h.
| #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
Definition at line 9236 of file stm32f4xx.h.
| #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000) |
Definition at line 9245 of file stm32f4xx.h.
| #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040) |
Definition at line 9230 of file stm32f4xx.h.
| #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000) |
Definition at line 9238 of file stm32f4xx.h.
| #define RCC_CR_CSSON ((uint32_t)0x00080000) |
Definition at line 9073 of file stm32f4xx.h.
| #define RCC_CR_HSEBYP ((uint32_t)0x00040000) |
Definition at line 9072 of file stm32f4xx.h.
Referenced by SetSysClock().
| #define RCC_CR_HSEON ((uint32_t)0x00010000) |
Definition at line 9070 of file stm32f4xx.h.
Referenced by SetSysClock().
| #define RCC_CR_HSERDY ((uint32_t)0x00020000) |
Definition at line 9071 of file stm32f4xx.h.
Referenced by SetSysClock().
| #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
Definition at line 9060 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100 |
Bit 0
Definition at line 9061 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200 |
Bit 1
Definition at line 9062 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400 |
Bit 2
Definition at line 9063 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800 |
Bit 3
Definition at line 9064 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000 |
Bit 4
Definition at line 9065 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000 |
Bit 5
Definition at line 9066 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000 |
Bit 6
Definition at line 9067 of file stm32f4xx.h.
| #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000 |
Bit 7
Definition at line 9068 of file stm32f4xx.h.
| #define RCC_CR_HSION ((uint32_t)0x00000001) |
Definition at line 9050 of file stm32f4xx.h.
| #define RCC_CR_HSIRDY ((uint32_t)0x00000002) |
Definition at line 9051 of file stm32f4xx.h.
| #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
Definition at line 9053 of file stm32f4xx.h.
| #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008 |
Bit 0
Definition at line 9054 of file stm32f4xx.h.
| #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010 |
Bit 1
Definition at line 9055 of file stm32f4xx.h.
| #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020 |
Bit 2
Definition at line 9056 of file stm32f4xx.h.
| #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040 |
Bit 3
Definition at line 9057 of file stm32f4xx.h.
| #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080 |
Bit 4
Definition at line 9058 of file stm32f4xx.h.
| #define RCC_CR_PLLI2SON ((uint32_t)0x04000000) |
Definition at line 9076 of file stm32f4xx.h.
| #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000) |
Definition at line 9077 of file stm32f4xx.h.
| #define RCC_CR_PLLON ((uint32_t)0x01000000) |
Definition at line 9074 of file stm32f4xx.h.
Referenced by SetSysClock().
| #define RCC_CR_PLLRDY ((uint32_t)0x02000000) |
Definition at line 9075 of file stm32f4xx.h.
Referenced by SetSysClock().
| #define RCC_CR_PLLSAION ((uint32_t)0x10000000) |
Definition at line 9078 of file stm32f4xx.h.
| #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000) |
Definition at line 9079 of file stm32f4xx.h.
| #define RCC_CSR_BORRSTF ((uint32_t)0x02000000) |
Definition at line 9619 of file stm32f4xx.h.
| #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
Definition at line 9625 of file stm32f4xx.h.
| #define RCC_CSR_LSION ((uint32_t)0x00000001) |
Definition at line 9616 of file stm32f4xx.h.
| #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
Definition at line 9617 of file stm32f4xx.h.
| #define RCC_CSR_PADRSTF ((uint32_t)0x04000000) |
Definition at line 9620 of file stm32f4xx.h.
| #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
Definition at line 9621 of file stm32f4xx.h.
| #define RCC_CSR_RMVF ((uint32_t)0x01000000) |
Definition at line 9618 of file stm32f4xx.h.
Referenced by RCC_ClearFlag().
| #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
Definition at line 9622 of file stm32f4xx.h.
| #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000) |
Definition at line 9623 of file stm32f4xx.h.
| #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
Definition at line 9624 of file stm32f4xx.h.
| #define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F) |
Definition at line 9714 of file stm32f4xx.h.
Referenced by RCC_SAIPLLI2SClkDivConfig().
| #define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00) |
Definition at line 9715 of file stm32f4xx.h.
Referenced by RCC_SAIPLLSAIClkDivConfig().
| #define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000) |
Definition at line 9716 of file stm32f4xx.h.
| #define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000) |
Definition at line 9740 of file stm32f4xx.h.
| #define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000) |
Definition at line 9741 of file stm32f4xx.h.
| #define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000) |
Definition at line 9742 of file stm32f4xx.h.
| #define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000) |
Definition at line 9749 of file stm32f4xx.h.
| #define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000) |
Definition at line 9750 of file stm32f4xx.h.
| #define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000) |
Definition at line 9751 of file stm32f4xx.h.
| #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000) |
Definition at line 9758 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F) |
Definition at line 9082 of file stm32f4xx.h.
Referenced by I2S_Init(), RCC_GetClocksFreq(), and SystemCoreClockUpdate().
| #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001) |
Definition at line 9083 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002) |
Definition at line 9084 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004) |
Definition at line 9085 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008) |
Definition at line 9086 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010) |
Definition at line 9087 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020) |
Definition at line 9088 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0) |
Definition at line 9090 of file stm32f4xx.h.
Referenced by RCC_GetClocksFreq(), and SystemCoreClockUpdate().
| #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040) |
Definition at line 9091 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080) |
Definition at line 9092 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100) |
Definition at line 9093 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200) |
Definition at line 9094 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400) |
Definition at line 9095 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800) |
Definition at line 9096 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000) |
Definition at line 9097 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000) |
Definition at line 9098 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000) |
Definition at line 9099 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000) |
Definition at line 9101 of file stm32f4xx.h.
Referenced by RCC_GetClocksFreq(), and SystemCoreClockUpdate().
| #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000) |
Definition at line 9102 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000) |
Definition at line 9103 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000) |
Definition at line 9109 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000) |
Definition at line 9110 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000) |
Definition at line 9111 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000) |
Definition at line 9112 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000) |
Definition at line 9113 of file stm32f4xx.h.
| #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000) |
Definition at line 9105 of file stm32f4xx.h.
Referenced by I2S_Init(), RCC_GetClocksFreq(), and SystemCoreClockUpdate().
| #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000) |
Definition at line 9106 of file stm32f4xx.h.
Referenced by I2S_Init(), and SetSysClock().
| #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000) |
Definition at line 9107 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F) |
Definition at line 9634 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001) |
Definition at line 9635 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002) |
Definition at line 9636 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004) |
Definition at line 9637 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008) |
Definition at line 9638 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010) |
Definition at line 9639 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020) |
Definition at line 9640 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0) |
Definition at line 9642 of file stm32f4xx.h.
Referenced by I2S_Init().
| #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040) |
Definition at line 9643 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080) |
Definition at line 9644 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100) |
Definition at line 9645 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200) |
Definition at line 9646 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400) |
Definition at line 9647 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800) |
Definition at line 9648 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000) |
Definition at line 9649 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000) |
Definition at line 9650 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000) |
Definition at line 9651 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000) |
Definition at line 9663 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000) |
Definition at line 9664 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000) |
Definition at line 9665 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000) |
Definition at line 9666 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000) |
Definition at line 9667 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000) |
Definition at line 9669 of file stm32f4xx.h.
Referenced by I2S_Init().
| #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000) |
Definition at line 9670 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000) |
Definition at line 9671 of file stm32f4xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000) |
Definition at line 9672 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0) |
Definition at line 9685 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040) |
Definition at line 9686 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080) |
Definition at line 9687 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100) |
Definition at line 9688 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200) |
Definition at line 9689 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400) |
Definition at line 9690 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800) |
Definition at line 9691 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000) |
Definition at line 9692 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000) |
Definition at line 9693 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000) |
Definition at line 9694 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000) |
Definition at line 9702 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000) |
Definition at line 9703 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000) |
Definition at line 9704 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000) |
Definition at line 9705 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000) |
Definition at line 9706 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000) |
Definition at line 9708 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000) |
Definition at line 9709 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000) |
Definition at line 9710 of file stm32f4xx.h.
| #define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000) |
Definition at line 9711 of file stm32f4xx.h.
| #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000) |
Definition at line 9629 of file stm32f4xx.h.
| #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF) |
Definition at line 9628 of file stm32f4xx.h.
| #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000) |
Definition at line 9630 of file stm32f4xx.h.
| #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000) |
Definition at line 9631 of file stm32f4xx.h.
| #define RNG_CR_IE ((uint32_t)0x00000008) |
Definition at line 9824 of file stm32f4xx.h.
| #define RNG_CR_RNGEN ((uint32_t)0x00000004) |
Definition at line 9823 of file stm32f4xx.h.
| #define RNG_SR_CECS ((uint32_t)0x00000002) |
Definition at line 9828 of file stm32f4xx.h.
| #define RNG_SR_CEIS ((uint32_t)0x00000020) |
Definition at line 9830 of file stm32f4xx.h.
| #define RNG_SR_DRDY ((uint32_t)0x00000001) |
Definition at line 9827 of file stm32f4xx.h.
| #define RNG_SR_SECS ((uint32_t)0x00000004) |
Definition at line 9829 of file stm32f4xx.h.
| #define RNG_SR_SEIS ((uint32_t)0x00000040) |
Definition at line 9831 of file stm32f4xx.h.
| #define RTC_ALRMAR_DT ((uint32_t)0x30000000) |
Definition at line 9957 of file stm32f4xx.h.
Referenced by RTC_GetAlarm().
| #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) |
Definition at line 9958 of file stm32f4xx.h.
| #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) |
Definition at line 9959 of file stm32f4xx.h.
| #define RTC_ALRMAR_DU ((uint32_t)0x0F000000) |
Definition at line 9960 of file stm32f4xx.h.
Referenced by RTC_GetAlarm().
| #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) |
Definition at line 9961 of file stm32f4xx.h.
| #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) |
Definition at line 9962 of file stm32f4xx.h.
| #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) |
Definition at line 9963 of file stm32f4xx.h.
| #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) |
Definition at line 9964 of file stm32f4xx.h.
| #define RTC_ALRMAR_HT ((uint32_t)0x00300000) |
Definition at line 9967 of file stm32f4xx.h.
Referenced by RTC_GetAlarm().
| #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) |
Definition at line 9968 of file stm32f4xx.h.
| #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) |
Definition at line 9969 of file stm32f4xx.h.
| #define RTC_ALRMAR_HU ((uint32_t)0x000F0000) |
Definition at line 9970 of file stm32f4xx.h.
Referenced by RTC_GetAlarm().
| #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) |
Definition at line 9971 of file stm32f4xx.h.
| #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) |
Definition at line 9972 of file stm32f4xx.h.
| #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) |
Definition at line 9973 of file stm32f4xx.h.
| #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) |
Definition at line 9974 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNT ((uint32_t)0x00007000) |
Definition at line 9976 of file stm32f4xx.h.
Referenced by RTC_GetAlarm().
| #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) |
Definition at line 9977 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) |
Definition at line 9978 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) |
Definition at line 9979 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) |
Definition at line 9980 of file stm32f4xx.h.
Referenced by RTC_GetAlarm().
| #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) |
Definition at line 9981 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) |
Definition at line 9982 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) |
Definition at line 9983 of file stm32f4xx.h.
| #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) |
Definition at line 9984 of file stm32f4xx.h.
| #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) |
Definition at line 9985 of file stm32f4xx.h.
| #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) |
Definition at line 9975 of file stm32f4xx.h.
| #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) |
Definition at line 9965 of file stm32f4xx.h.
| #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) |
Definition at line 9955 of file stm32f4xx.h.
| #define RTC_ALRMAR_PM ((uint32_t)0x00400000) |
Definition at line 9966 of file stm32f4xx.h.
Referenced by RTC_GetAlarm().
| #define RTC_ALRMAR_ST ((uint32_t)0x00000070) |
Definition at line 9986 of file stm32f4xx.h.
Referenced by RTC_GetAlarm().
| #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) |
Definition at line 9987 of file stm32f4xx.h.
| #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) |
Definition at line 9988 of file stm32f4xx.h.
| #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) |
Definition at line 9989 of file stm32f4xx.h.
| #define RTC_ALRMAR_SU ((uint32_t)0x0000000F) |
Definition at line 9990 of file stm32f4xx.h.
Referenced by RTC_GetAlarm().
| #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) |
Definition at line 9991 of file stm32f4xx.h.
| #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) |
Definition at line 9992 of file stm32f4xx.h.
| #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) |
Definition at line 9993 of file stm32f4xx.h.
| #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) |
Definition at line 9994 of file stm32f4xx.h.
| #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) |
Definition at line 9956 of file stm32f4xx.h.
Referenced by RTC_GetAlarm().
| #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) |
Definition at line 10138 of file stm32f4xx.h.
| #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) |
Definition at line 10139 of file stm32f4xx.h.
| #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) |
Definition at line 10140 of file stm32f4xx.h.
| #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) |
Definition at line 10141 of file stm32f4xx.h.
| #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) |
Definition at line 10142 of file stm32f4xx.h.
| #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) |
Definition at line 10143 of file stm32f4xx.h.
Referenced by RTC_GetAlarmSubSecond().
| #define RTC_ALRMBR_DT ((uint32_t)0x30000000) |
Definition at line 9999 of file stm32f4xx.h.
| #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) |
Definition at line 10000 of file stm32f4xx.h.
| #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) |
Definition at line 10001 of file stm32f4xx.h.
| #define RTC_ALRMBR_DU ((uint32_t)0x0F000000) |
Definition at line 10002 of file stm32f4xx.h.
| #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) |
Definition at line 10003 of file stm32f4xx.h.
| #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) |
Definition at line 10004 of file stm32f4xx.h.
| #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) |
Definition at line 10005 of file stm32f4xx.h.
| #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) |
Definition at line 10006 of file stm32f4xx.h.
| #define RTC_ALRMBR_HT ((uint32_t)0x00300000) |
Definition at line 10009 of file stm32f4xx.h.
| #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) |
Definition at line 10010 of file stm32f4xx.h.
| #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) |
Definition at line 10011 of file stm32f4xx.h.
| #define RTC_ALRMBR_HU ((uint32_t)0x000F0000) |
Definition at line 10012 of file stm32f4xx.h.
| #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) |
Definition at line 10013 of file stm32f4xx.h.
| #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) |
Definition at line 10014 of file stm32f4xx.h.
| #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) |
Definition at line 10015 of file stm32f4xx.h.
| #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) |
Definition at line 10016 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNT ((uint32_t)0x00007000) |
Definition at line 10018 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) |
Definition at line 10019 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) |
Definition at line 10020 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) |
Definition at line 10021 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) |
Definition at line 10022 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) |
Definition at line 10023 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) |
Definition at line 10024 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) |
Definition at line 10025 of file stm32f4xx.h.
| #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) |
Definition at line 10026 of file stm32f4xx.h.
| #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) |
Definition at line 10027 of file stm32f4xx.h.
| #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) |
Definition at line 10017 of file stm32f4xx.h.
| #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) |
Definition at line 10007 of file stm32f4xx.h.
| #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) |
Definition at line 9997 of file stm32f4xx.h.
| #define RTC_ALRMBR_PM ((uint32_t)0x00400000) |
Definition at line 10008 of file stm32f4xx.h.
| #define RTC_ALRMBR_ST ((uint32_t)0x00000070) |
Definition at line 10028 of file stm32f4xx.h.
| #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) |
Definition at line 10029 of file stm32f4xx.h.
| #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) |
Definition at line 10030 of file stm32f4xx.h.
| #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) |
Definition at line 10031 of file stm32f4xx.h.
| #define RTC_ALRMBR_SU ((uint32_t)0x0000000F) |
Definition at line 10032 of file stm32f4xx.h.
| #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) |
Definition at line 10033 of file stm32f4xx.h.
| #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) |
Definition at line 10034 of file stm32f4xx.h.
| #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) |
Definition at line 10035 of file stm32f4xx.h.
| #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) |
Definition at line 10036 of file stm32f4xx.h.
| #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) |
Definition at line 9998 of file stm32f4xx.h.
| #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) |
Definition at line 10146 of file stm32f4xx.h.
| #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) |
Definition at line 10147 of file stm32f4xx.h.
| #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) |
Definition at line 10148 of file stm32f4xx.h.
| #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) |
Definition at line 10149 of file stm32f4xx.h.
| #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) |
Definition at line 10150 of file stm32f4xx.h.
| #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) |
Definition at line 10151 of file stm32f4xx.h.
Referenced by RTC_GetAlarmSubSecond().
| #define RTC_BKP0R ((uint32_t)0xFFFFFFFF) |
Definition at line 10154 of file stm32f4xx.h.
| #define RTC_BKP10R ((uint32_t)0xFFFFFFFF) |
Definition at line 10184 of file stm32f4xx.h.
| #define RTC_BKP11R ((uint32_t)0xFFFFFFFF) |
Definition at line 10187 of file stm32f4xx.h.
| #define RTC_BKP12R ((uint32_t)0xFFFFFFFF) |
Definition at line 10190 of file stm32f4xx.h.
| #define RTC_BKP13R ((uint32_t)0xFFFFFFFF) |
Definition at line 10193 of file stm32f4xx.h.
| #define RTC_BKP14R ((uint32_t)0xFFFFFFFF) |
Definition at line 10196 of file stm32f4xx.h.
| #define RTC_BKP15R ((uint32_t)0xFFFFFFFF) |
Definition at line 10199 of file stm32f4xx.h.
| #define RTC_BKP16R ((uint32_t)0xFFFFFFFF) |
Definition at line 10202 of file stm32f4xx.h.
| #define RTC_BKP17R ((uint32_t)0xFFFFFFFF) |
Definition at line 10205 of file stm32f4xx.h.
| #define RTC_BKP18R ((uint32_t)0xFFFFFFFF) |
Definition at line 10208 of file stm32f4xx.h.
| #define RTC_BKP19R ((uint32_t)0xFFFFFFFF) |
Definition at line 10211 of file stm32f4xx.h.
| #define RTC_BKP1R ((uint32_t)0xFFFFFFFF) |
Definition at line 10157 of file stm32f4xx.h.
| #define RTC_BKP2R ((uint32_t)0xFFFFFFFF) |
Definition at line 10160 of file stm32f4xx.h.
| #define RTC_BKP3R ((uint32_t)0xFFFFFFFF) |
Definition at line 10163 of file stm32f4xx.h.
| #define RTC_BKP4R ((uint32_t)0xFFFFFFFF) |
Definition at line 10166 of file stm32f4xx.h.
| #define RTC_BKP5R ((uint32_t)0xFFFFFFFF) |
Definition at line 10169 of file stm32f4xx.h.
| #define RTC_BKP6R ((uint32_t)0xFFFFFFFF) |
Definition at line 10172 of file stm32f4xx.h.
| #define RTC_BKP7R ((uint32_t)0xFFFFFFFF) |
Definition at line 10175 of file stm32f4xx.h.
| #define RTC_BKP8R ((uint32_t)0xFFFFFFFF) |
Definition at line 10178 of file stm32f4xx.h.
| #define RTC_BKP9R ((uint32_t)0xFFFFFFFF) |
Definition at line 10181 of file stm32f4xx.h.
| #define RTC_CALIBR_DC ((uint32_t)0x0000001F) |
Definition at line 9952 of file stm32f4xx.h.
| #define RTC_CALIBR_DCS ((uint32_t)0x00000080) |
Definition at line 9951 of file stm32f4xx.h.
| #define RTC_CALR_CALM ((uint32_t)0x000001FF) |
Definition at line 10104 of file stm32f4xx.h.
| #define RTC_CALR_CALM_0 ((uint32_t)0x00000001) |
Definition at line 10105 of file stm32f4xx.h.
| #define RTC_CALR_CALM_1 ((uint32_t)0x00000002) |
Definition at line 10106 of file stm32f4xx.h.
| #define RTC_CALR_CALM_2 ((uint32_t)0x00000004) |
Definition at line 10107 of file stm32f4xx.h.
| #define RTC_CALR_CALM_3 ((uint32_t)0x00000008) |
Definition at line 10108 of file stm32f4xx.h.
| #define RTC_CALR_CALM_4 ((uint32_t)0x00000010) |
Definition at line 10109 of file stm32f4xx.h.
| #define RTC_CALR_CALM_5 ((uint32_t)0x00000020) |
Definition at line 10110 of file stm32f4xx.h.
| #define RTC_CALR_CALM_6 ((uint32_t)0x00000040) |
Definition at line 10111 of file stm32f4xx.h.
| #define RTC_CALR_CALM_7 ((uint32_t)0x00000080) |
Definition at line 10112 of file stm32f4xx.h.
| #define RTC_CALR_CALM_8 ((uint32_t)0x00000100) |
Definition at line 10113 of file stm32f4xx.h.
| #define RTC_CALR_CALP ((uint32_t)0x00008000) |
Definition at line 10101 of file stm32f4xx.h.
| #define RTC_CALR_CALW16 ((uint32_t)0x00002000) |
Definition at line 10103 of file stm32f4xx.h.
| #define RTC_CALR_CALW8 ((uint32_t)0x00004000) |
Definition at line 10102 of file stm32f4xx.h.
| #define RTC_CR_ADD1H ((uint32_t)0x00010000) |
Definition at line 9906 of file stm32f4xx.h.
| #define RTC_CR_ALRAE ((uint32_t)0x00000100) |
Definition at line 9914 of file stm32f4xx.h.
| #define RTC_CR_ALRAIE ((uint32_t)0x00001000) |
Definition at line 9910 of file stm32f4xx.h.
| #define RTC_CR_ALRBE ((uint32_t)0x00000200) |
Definition at line 9913 of file stm32f4xx.h.
| #define RTC_CR_ALRBIE ((uint32_t)0x00002000) |
Definition at line 9909 of file stm32f4xx.h.
| #define RTC_CR_BCK ((uint32_t)0x00040000) |
Definition at line 9904 of file stm32f4xx.h.
Referenced by RTC_DayLightSavingConfig(), and RTC_GetStoreOperation().
| #define RTC_CR_BYPSHAD ((uint32_t)0x00000020) |
Definition at line 9917 of file stm32f4xx.h.
Referenced by RTC_BypassShadowCmd(), RTC_SetDate(), and RTC_SetTime().
| #define RTC_CR_COE ((uint32_t)0x00800000) |
Definition at line 9898 of file stm32f4xx.h.
Referenced by RTC_CalibOutputCmd().
| #define RTC_CR_COSEL ((uint32_t)0x00080000) |
Definition at line 9903 of file stm32f4xx.h.
Referenced by RTC_CalibOutputConfig().
| #define RTC_CR_DCE ((uint32_t)0x00000080) |
Definition at line 9915 of file stm32f4xx.h.
Referenced by RTC_CoarseCalibCmd().
| #define RTC_CR_FMT ((uint32_t)0x00000040) |
Definition at line 9916 of file stm32f4xx.h.
Referenced by RTC_Init(), RTC_SetAlarm(), and RTC_SetTime().
| #define RTC_CR_OSEL ((uint32_t)0x00600000) |
Definition at line 9899 of file stm32f4xx.h.
Referenced by RTC_OutputConfig().
| #define RTC_CR_OSEL_0 ((uint32_t)0x00200000) |
Definition at line 9900 of file stm32f4xx.h.
| #define RTC_CR_OSEL_1 ((uint32_t)0x00400000) |
Definition at line 9901 of file stm32f4xx.h.
| #define RTC_CR_POL ((uint32_t)0x00100000) |
Definition at line 9902 of file stm32f4xx.h.
Referenced by RTC_OutputConfig().
| #define RTC_CR_REFCKON ((uint32_t)0x00000010) |
Definition at line 9918 of file stm32f4xx.h.
Referenced by RTC_RefClockCmd(), and RTC_SynchroShiftConfig().
| #define RTC_CR_SUB1H ((uint32_t)0x00020000) |
Definition at line 9905 of file stm32f4xx.h.
| #define RTC_CR_TSE ((uint32_t)0x00000800) |
Definition at line 9911 of file stm32f4xx.h.
Referenced by RTC_TimeStampCmd().
| #define RTC_CR_TSEDGE ((uint32_t)0x00000008) |
Definition at line 9919 of file stm32f4xx.h.
Referenced by RTC_TimeStampCmd().
| #define RTC_CR_TSIE ((uint32_t)0x00008000) |
Definition at line 9907 of file stm32f4xx.h.
| #define RTC_CR_WUCKSEL ((uint32_t)0x00000007) |
Definition at line 9920 of file stm32f4xx.h.
Referenced by RTC_WakeUpClockConfig().
| #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) |
Definition at line 9921 of file stm32f4xx.h.
| #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) |
Definition at line 9922 of file stm32f4xx.h.
| #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) |
Definition at line 9923 of file stm32f4xx.h.
| #define RTC_CR_WUTE ((uint32_t)0x00000400) |
Definition at line 9912 of file stm32f4xx.h.
Referenced by RTC_WakeUpCmd().
| #define RTC_CR_WUTIE ((uint32_t)0x00004000) |
Definition at line 9908 of file stm32f4xx.h.
| #define RTC_DR_DT ((uint32_t)0x00000030) |
Definition at line 9888 of file stm32f4xx.h.
Referenced by RTC_GetDate(), and RTC_GetTimeStamp().
| #define RTC_DR_DT_0 ((uint32_t)0x00000010) |
Definition at line 9889 of file stm32f4xx.h.
| #define RTC_DR_DT_1 ((uint32_t)0x00000020) |
Definition at line 9890 of file stm32f4xx.h.
| #define RTC_DR_DU ((uint32_t)0x0000000F) |
Definition at line 9891 of file stm32f4xx.h.
Referenced by RTC_GetDate(), and RTC_GetTimeStamp().
| #define RTC_DR_DU_0 ((uint32_t)0x00000001) |
Definition at line 9892 of file stm32f4xx.h.
| #define RTC_DR_DU_1 ((uint32_t)0x00000002) |
Definition at line 9893 of file stm32f4xx.h.
| #define RTC_DR_DU_2 ((uint32_t)0x00000004) |
Definition at line 9894 of file stm32f4xx.h.
| #define RTC_DR_DU_3 ((uint32_t)0x00000008) |
Definition at line 9895 of file stm32f4xx.h.
| #define RTC_DR_MT ((uint32_t)0x00001000) |
Definition at line 9882 of file stm32f4xx.h.
Referenced by RTC_GetDate(), and RTC_GetTimeStamp().
| #define RTC_DR_MU ((uint32_t)0x00000F00) |
Definition at line 9883 of file stm32f4xx.h.
Referenced by RTC_GetDate(), and RTC_GetTimeStamp().
| #define RTC_DR_MU_0 ((uint32_t)0x00000100) |
Definition at line 9884 of file stm32f4xx.h.
| #define RTC_DR_MU_1 ((uint32_t)0x00000200) |
Definition at line 9885 of file stm32f4xx.h.
| #define RTC_DR_MU_2 ((uint32_t)0x00000400) |
Definition at line 9886 of file stm32f4xx.h.
| #define RTC_DR_MU_3 ((uint32_t)0x00000800) |
Definition at line 9887 of file stm32f4xx.h.
| #define RTC_DR_WDU ((uint32_t)0x0000E000) |
Definition at line 9878 of file stm32f4xx.h.
Referenced by RTC_GetDate(), and RTC_GetTimeStamp().
| #define RTC_DR_WDU_0 ((uint32_t)0x00002000) |
Definition at line 9879 of file stm32f4xx.h.
| #define RTC_DR_WDU_1 ((uint32_t)0x00004000) |
Definition at line 9880 of file stm32f4xx.h.
| #define RTC_DR_WDU_2 ((uint32_t)0x00008000) |
Definition at line 9881 of file stm32f4xx.h.
| #define RTC_DR_YT ((uint32_t)0x00F00000) |
Definition at line 9868 of file stm32f4xx.h.
Referenced by RTC_GetDate().
| #define RTC_DR_YT_0 ((uint32_t)0x00100000) |
Definition at line 9869 of file stm32f4xx.h.
| #define RTC_DR_YT_1 ((uint32_t)0x00200000) |
Definition at line 9870 of file stm32f4xx.h.
| #define RTC_DR_YT_2 ((uint32_t)0x00400000) |
Definition at line 9871 of file stm32f4xx.h.
| #define RTC_DR_YT_3 ((uint32_t)0x00800000) |
Definition at line 9872 of file stm32f4xx.h.
| #define RTC_DR_YU ((uint32_t)0x000F0000) |
Definition at line 9873 of file stm32f4xx.h.
Referenced by RTC_GetDate().
| #define RTC_DR_YU_0 ((uint32_t)0x00010000) |
Definition at line 9874 of file stm32f4xx.h.
| #define RTC_DR_YU_1 ((uint32_t)0x00020000) |
Definition at line 9875 of file stm32f4xx.h.
| #define RTC_DR_YU_2 ((uint32_t)0x00040000) |
Definition at line 9876 of file stm32f4xx.h.
| #define RTC_DR_YU_3 ((uint32_t)0x00080000) |
Definition at line 9877 of file stm32f4xx.h.
| #define RTC_ISR_ALRAF ((uint32_t)0x00000100) |
Definition at line 9933 of file stm32f4xx.h.
| #define RTC_ISR_ALRAWF ((uint32_t)0x00000001) |
Definition at line 9941 of file stm32f4xx.h.
| #define RTC_ISR_ALRBF ((uint32_t)0x00000200) |
Definition at line 9932 of file stm32f4xx.h.
| #define RTC_ISR_ALRBWF ((uint32_t)0x00000002) |
Definition at line 9940 of file stm32f4xx.h.
| #define RTC_ISR_INIT ((uint32_t)0x00000080) |
Definition at line 9934 of file stm32f4xx.h.
Referenced by RTC_ClearFlag(), RTC_ClearITPendingBit(), and RTC_ExitInitMode().
| #define RTC_ISR_INITF ((uint32_t)0x00000040) |
Definition at line 9935 of file stm32f4xx.h.
Referenced by RTC_EnterInitMode().
| #define RTC_ISR_INITS ((uint32_t)0x00000010) |
Definition at line 9937 of file stm32f4xx.h.
| #define RTC_ISR_RECALPF ((uint32_t)0x00010000) |
Definition at line 9926 of file stm32f4xx.h.
Referenced by RTC_SmoothCalibConfig().
| #define RTC_ISR_RSF ((uint32_t)0x00000020) |
Definition at line 9936 of file stm32f4xx.h.
Referenced by RTC_WaitForSynchro().
| #define RTC_ISR_SHPF ((uint32_t)0x00000008) |
Definition at line 9938 of file stm32f4xx.h.
Referenced by RTC_SynchroShiftConfig().
| #define RTC_ISR_TAMP1F ((uint32_t)0x00002000) |
Definition at line 9927 of file stm32f4xx.h.
| #define RTC_ISR_TAMP2F ((uint32_t)0x00004000) |
Definition at line 9928 of file stm32f4xx.h.
| #define RTC_ISR_TSF ((uint32_t)0x00000800) |
Definition at line 9930 of file stm32f4xx.h.
| #define RTC_ISR_TSOVF ((uint32_t)0x00001000) |
Definition at line 9929 of file stm32f4xx.h.
| #define RTC_ISR_WUTF ((uint32_t)0x00000400) |
Definition at line 9931 of file stm32f4xx.h.
| #define RTC_ISR_WUTWF ((uint32_t)0x00000004) |
Definition at line 9939 of file stm32f4xx.h.
Referenced by RTC_DeInit(), and RTC_WakeUpCmd().
| #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) |
Definition at line 9944 of file stm32f4xx.h.
| #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF) |
Definition at line 9945 of file stm32f4xx.h.
| #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) |
Definition at line 10046 of file stm32f4xx.h.
| #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) |
Definition at line 10045 of file stm32f4xx.h.
| #define RTC_SSR_SS ((uint32_t)0x0000FFFF) |
Definition at line 10042 of file stm32f4xx.h.
| #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) |
Definition at line 10116 of file stm32f4xx.h.
Referenced by RTC_OutputTypeConfig().
| #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) |
Definition at line 10135 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) |
Definition at line 10134 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) |
Definition at line 10132 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010) |
Definition at line 10131 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) |
Definition at line 10123 of file stm32f4xx.h.
Referenced by RTC_TamperFilterConfig().
| #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) |
Definition at line 10124 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) |
Definition at line 10125 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) |
Definition at line 10126 of file stm32f4xx.h.
Referenced by RTC_TamperSamplingFreqConfig().
| #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) |
Definition at line 10127 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) |
Definition at line 10128 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) |
Definition at line 10129 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) |
Definition at line 10133 of file stm32f4xx.h.
Referenced by RTC_GetITStatus(), and RTC_ITConfig().
| #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000) |
Definition at line 10118 of file stm32f4xx.h.
Referenced by RTC_TamperPinSelection().
| #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) |
Definition at line 10120 of file stm32f4xx.h.
Referenced by RTC_TamperPinsPrechargeDuration().
| #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) |
Definition at line 10121 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) |
Definition at line 10122 of file stm32f4xx.h.
| #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) |
Definition at line 10119 of file stm32f4xx.h.
Referenced by RTC_TamperPullUpCmd().
| #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) |
Definition at line 10130 of file stm32f4xx.h.
Referenced by RTC_TimeStampOnTamperDetectionCmd().
| #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000) |
Definition at line 10117 of file stm32f4xx.h.
Referenced by RTC_TimeStampPinSelection().
| #define RTC_TR_HT ((uint32_t)0x00300000) |
Definition at line 9840 of file stm32f4xx.h.
Referenced by RTC_GetTime(), and RTC_GetTimeStamp().
| #define RTC_TR_HT_0 ((uint32_t)0x00100000) |
Definition at line 9841 of file stm32f4xx.h.
| #define RTC_TR_HT_1 ((uint32_t)0x00200000) |
Definition at line 9842 of file stm32f4xx.h.
| #define RTC_TR_HU ((uint32_t)0x000F0000) |
Definition at line 9843 of file stm32f4xx.h.
Referenced by RTC_GetTime(), and RTC_GetTimeStamp().
| #define RTC_TR_HU_0 ((uint32_t)0x00010000) |
Definition at line 9844 of file stm32f4xx.h.
| #define RTC_TR_HU_1 ((uint32_t)0x00020000) |
Definition at line 9845 of file stm32f4xx.h.
| #define RTC_TR_HU_2 ((uint32_t)0x00040000) |
Definition at line 9846 of file stm32f4xx.h.
| #define RTC_TR_HU_3 ((uint32_t)0x00080000) |
Definition at line 9847 of file stm32f4xx.h.
| #define RTC_TR_MNT ((uint32_t)0x00007000) |
Definition at line 9848 of file stm32f4xx.h.
Referenced by RTC_GetTime(), and RTC_GetTimeStamp().
| #define RTC_TR_MNT_0 ((uint32_t)0x00001000) |
Definition at line 9849 of file stm32f4xx.h.
| #define RTC_TR_MNT_1 ((uint32_t)0x00002000) |
Definition at line 9850 of file stm32f4xx.h.
| #define RTC_TR_MNT_2 ((uint32_t)0x00004000) |
Definition at line 9851 of file stm32f4xx.h.
| #define RTC_TR_MNU ((uint32_t)0x00000F00) |
Definition at line 9852 of file stm32f4xx.h.
Referenced by RTC_GetTime(), and RTC_GetTimeStamp().
| #define RTC_TR_MNU_0 ((uint32_t)0x00000100) |
Definition at line 9853 of file stm32f4xx.h.
| #define RTC_TR_MNU_1 ((uint32_t)0x00000200) |
Definition at line 9854 of file stm32f4xx.h.
| #define RTC_TR_MNU_2 ((uint32_t)0x00000400) |
Definition at line 9855 of file stm32f4xx.h.
| #define RTC_TR_MNU_3 ((uint32_t)0x00000800) |
Definition at line 9856 of file stm32f4xx.h.
| #define RTC_TR_PM ((uint32_t)0x00400000) |
Definition at line 9839 of file stm32f4xx.h.
Referenced by RTC_GetTime(), and RTC_GetTimeStamp().
| #define RTC_TR_ST ((uint32_t)0x00000070) |
Definition at line 9857 of file stm32f4xx.h.
Referenced by RTC_GetTime(), and RTC_GetTimeStamp().
| #define RTC_TR_ST_0 ((uint32_t)0x00000010) |
Definition at line 9858 of file stm32f4xx.h.
| #define RTC_TR_ST_1 ((uint32_t)0x00000020) |
Definition at line 9859 of file stm32f4xx.h.
| #define RTC_TR_ST_2 ((uint32_t)0x00000040) |
Definition at line 9860 of file stm32f4xx.h.
| #define RTC_TR_SU ((uint32_t)0x0000000F) |
Definition at line 9861 of file stm32f4xx.h.
Referenced by RTC_GetTime(), and RTC_GetTimeStamp().
| #define RTC_TR_SU_0 ((uint32_t)0x00000001) |
Definition at line 9862 of file stm32f4xx.h.
| #define RTC_TR_SU_1 ((uint32_t)0x00000002) |
Definition at line 9863 of file stm32f4xx.h.
| #define RTC_TR_SU_2 ((uint32_t)0x00000004) |
Definition at line 9864 of file stm32f4xx.h.
| #define RTC_TR_SU_3 ((uint32_t)0x00000008) |
Definition at line 9865 of file stm32f4xx.h.
| #define RTC_TSDR_DT ((uint32_t)0x00000030) |
Definition at line 10088 of file stm32f4xx.h.
| #define RTC_TSDR_DT_0 ((uint32_t)0x00000010) |
Definition at line 10089 of file stm32f4xx.h.
| #define RTC_TSDR_DT_1 ((uint32_t)0x00000020) |
Definition at line 10090 of file stm32f4xx.h.
| #define RTC_TSDR_DU ((uint32_t)0x0000000F) |
Definition at line 10091 of file stm32f4xx.h.
| #define RTC_TSDR_DU_0 ((uint32_t)0x00000001) |
Definition at line 10092 of file stm32f4xx.h.
| #define RTC_TSDR_DU_1 ((uint32_t)0x00000002) |
Definition at line 10093 of file stm32f4xx.h.
| #define RTC_TSDR_DU_2 ((uint32_t)0x00000004) |
Definition at line 10094 of file stm32f4xx.h.
| #define RTC_TSDR_DU_3 ((uint32_t)0x00000008) |
Definition at line 10095 of file stm32f4xx.h.
| #define RTC_TSDR_MT ((uint32_t)0x00001000) |
Definition at line 10082 of file stm32f4xx.h.
| #define RTC_TSDR_MU ((uint32_t)0x00000F00) |
Definition at line 10083 of file stm32f4xx.h.
| #define RTC_TSDR_MU_0 ((uint32_t)0x00000100) |
Definition at line 10084 of file stm32f4xx.h.
| #define RTC_TSDR_MU_1 ((uint32_t)0x00000200) |
Definition at line 10085 of file stm32f4xx.h.
| #define RTC_TSDR_MU_2 ((uint32_t)0x00000400) |
Definition at line 10086 of file stm32f4xx.h.
| #define RTC_TSDR_MU_3 ((uint32_t)0x00000800) |
Definition at line 10087 of file stm32f4xx.h.
| #define RTC_TSDR_WDU ((uint32_t)0x0000E000) |
Definition at line 10078 of file stm32f4xx.h.
| #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) |
Definition at line 10079 of file stm32f4xx.h.
| #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) |
Definition at line 10080 of file stm32f4xx.h.
| #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) |
Definition at line 10081 of file stm32f4xx.h.
| #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF) |
Definition at line 10098 of file stm32f4xx.h.
| #define RTC_TSTR_HT ((uint32_t)0x00300000) |
Definition at line 10050 of file stm32f4xx.h.
| #define RTC_TSTR_HT_0 ((uint32_t)0x00100000) |
Definition at line 10051 of file stm32f4xx.h.
| #define RTC_TSTR_HT_1 ((uint32_t)0x00200000) |
Definition at line 10052 of file stm32f4xx.h.
| #define RTC_TSTR_HU ((uint32_t)0x000F0000) |
Definition at line 10053 of file stm32f4xx.h.
| #define RTC_TSTR_HU_0 ((uint32_t)0x00010000) |
Definition at line 10054 of file stm32f4xx.h.
| #define RTC_TSTR_HU_1 ((uint32_t)0x00020000) |
Definition at line 10055 of file stm32f4xx.h.
| #define RTC_TSTR_HU_2 ((uint32_t)0x00040000) |
Definition at line 10056 of file stm32f4xx.h.
| #define RTC_TSTR_HU_3 ((uint32_t)0x00080000) |
Definition at line 10057 of file stm32f4xx.h.
| #define RTC_TSTR_MNT ((uint32_t)0x00007000) |
Definition at line 10058 of file stm32f4xx.h.
| #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) |
Definition at line 10059 of file stm32f4xx.h.
| #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) |
Definition at line 10060 of file stm32f4xx.h.
| #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) |
Definition at line 10061 of file stm32f4xx.h.
| #define RTC_TSTR_MNU ((uint32_t)0x00000F00) |
Definition at line 10062 of file stm32f4xx.h.
| #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) |
Definition at line 10063 of file stm32f4xx.h.
| #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) |
Definition at line 10064 of file stm32f4xx.h.
| #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) |
Definition at line 10065 of file stm32f4xx.h.
| #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) |
Definition at line 10066 of file stm32f4xx.h.
| #define RTC_TSTR_PM ((uint32_t)0x00400000) |
Definition at line 10049 of file stm32f4xx.h.
| #define RTC_TSTR_ST ((uint32_t)0x00000070) |
Definition at line 10067 of file stm32f4xx.h.
| #define RTC_TSTR_ST_0 ((uint32_t)0x00000010) |
Definition at line 10068 of file stm32f4xx.h.
| #define RTC_TSTR_ST_1 ((uint32_t)0x00000020) |
Definition at line 10069 of file stm32f4xx.h.
| #define RTC_TSTR_ST_2 ((uint32_t)0x00000040) |
Definition at line 10070 of file stm32f4xx.h.
| #define RTC_TSTR_SU ((uint32_t)0x0000000F) |
Definition at line 10071 of file stm32f4xx.h.
| #define RTC_TSTR_SU_0 ((uint32_t)0x00000001) |
Definition at line 10072 of file stm32f4xx.h.
| #define RTC_TSTR_SU_1 ((uint32_t)0x00000002) |
Definition at line 10073 of file stm32f4xx.h.
| #define RTC_TSTR_SU_2 ((uint32_t)0x00000004) |
Definition at line 10074 of file stm32f4xx.h.
| #define RTC_TSTR_SU_3 ((uint32_t)0x00000008) |
Definition at line 10075 of file stm32f4xx.h.
| #define RTC_WPR_KEY ((uint32_t)0x000000FF) |
Definition at line 10039 of file stm32f4xx.h.
| #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) |
Definition at line 9948 of file stm32f4xx.h.
Referenced by RTC_GetWakeUpCounter().
| #define SAI_GCR_SYNCIN ((uint32_t)0x00000003) |
SYNCIN[1:0] bits (Synchronization Inputs)
Definition at line 10219 of file stm32f4xx.h.
| #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 10220 of file stm32f4xx.h.
| #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 10221 of file stm32f4xx.h.
| #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) |
SYNCOUT[1:0] bits (Synchronization Outputs)
Definition at line 10223 of file stm32f4xx.h.
| #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) |
Bit 0
Definition at line 10224 of file stm32f4xx.h.
| #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) |
Bit 1
Definition at line 10225 of file stm32f4xx.h.
| #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) |
Clear Anticipated frame synchronization detection
Definition at line 10359 of file stm32f4xx.h.
| #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) |
Clear Codec not ready
Definition at line 10358 of file stm32f4xx.h.
| #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) |
Clear FIFO request
Definition at line 10357 of file stm32f4xx.h.
| #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) |
Clear Late frame synchronization detection
Definition at line 10360 of file stm32f4xx.h.
| #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) |
Clear Mute detection
Definition at line 10355 of file stm32f4xx.h.
| #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) |
Clear Overrun underrun
Definition at line 10354 of file stm32f4xx.h.
| #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) |
Clear Wrong Clock Configuration
Definition at line 10356 of file stm32f4xx.h.
| #define SAI_xCR1_CKSTR ((uint32_t)0x00000200) |
ClocK STRobing edge
Definition at line 10242 of file stm32f4xx.h.
| #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) |
DMA enable
Definition at line 10251 of file stm32f4xx.h.
| #define SAI_xCR1_DS ((uint32_t)0x000000E0) |
DS[1:0] bits (Data Size)
Definition at line 10236 of file stm32f4xx.h.
| #define SAI_xCR1_DS_0 ((uint32_t)0x00000020) |
Bit 0
Definition at line 10237 of file stm32f4xx.h.
| #define SAI_xCR1_DS_1 ((uint32_t)0x00000040) |
Bit 1
Definition at line 10238 of file stm32f4xx.h.
| #define SAI_xCR1_DS_2 ((uint32_t)0x00000080) |
Bit 2
Definition at line 10239 of file stm32f4xx.h.
| #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) |
LSB First Configuration
Definition at line 10241 of file stm32f4xx.h.
| #define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) |
MCKDIV[3:0] (Master ClocK Divider)
Definition at line 10254 of file stm32f4xx.h.
| #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) |
Bit 0
Definition at line 10255 of file stm32f4xx.h.
| #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) |
Bit 1
Definition at line 10256 of file stm32f4xx.h.
| #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) |
Bit 2
Definition at line 10257 of file stm32f4xx.h.
| #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) |
Bit 3
Definition at line 10258 of file stm32f4xx.h.
| #define SAI_xCR1_MODE ((uint32_t)0x00000003) |
MODE[1:0] bits (Audio Block Mode)
Definition at line 10228 of file stm32f4xx.h.
| #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 10229 of file stm32f4xx.h.
| #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 10230 of file stm32f4xx.h.
| #define SAI_xCR1_MONO ((uint32_t)0x00001000) |
Mono mode
Definition at line 10248 of file stm32f4xx.h.
| #define SAI_xCR1_NODIV ((uint32_t)0x00080000) |
No Divider Configuration
Definition at line 10252 of file stm32f4xx.h.
| #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) |
Output Drive
Definition at line 10249 of file stm32f4xx.h.
| #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) |
PRTCFG[1:0] bits (Protocol Configuration)
Definition at line 10232 of file stm32f4xx.h.
| #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) |
Bit 0
Definition at line 10233 of file stm32f4xx.h.
| #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) |
Bit 1
Definition at line 10234 of file stm32f4xx.h.
| #define SAI_xCR1_SAIEN ((uint32_t)0x00010000) |
Audio Block enable
Definition at line 10250 of file stm32f4xx.h.
| #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) |
SYNCEN[1:0](SYNChronization ENable)
Definition at line 10244 of file stm32f4xx.h.
| #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) |
Bit 0
Definition at line 10245 of file stm32f4xx.h.
| #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) |
Bit 1
Definition at line 10246 of file stm32f4xx.h.
| #define SAI_xCR2_COMP ((uint32_t)0x0000C000) |
COMP[1:0] (Companding mode)
Definition at line 10280 of file stm32f4xx.h.
| #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) |
Bit 0
Definition at line 10281 of file stm32f4xx.h.
| #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) |
Bit 1
Definition at line 10282 of file stm32f4xx.h.
| #define SAI_xCR2_CPL ((uint32_t)0x00002000) |
Complement Bit
Definition at line 10278 of file stm32f4xx.h.
| #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) |
Fifo FLUSH
Definition at line 10265 of file stm32f4xx.h.
| #define SAI_xCR2_FTH ((uint32_t)0x00000003) |
FTH[1:0](Fifo THreshold)
Definition at line 10261 of file stm32f4xx.h.
| #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 10262 of file stm32f4xx.h.
| #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 10263 of file stm32f4xx.h.
| #define SAI_xCR2_MUTE ((uint32_t)0x00000020) |
Mute mode
Definition at line 10267 of file stm32f4xx.h.
| #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) |
MUTECNT[5:0] (MUTE counter)
Definition at line 10270 of file stm32f4xx.h.
| #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) |
Bit 0
Definition at line 10271 of file stm32f4xx.h.
| #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) |
Bit 1
Definition at line 10272 of file stm32f4xx.h.
| #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) |
Bit 2
Definition at line 10273 of file stm32f4xx.h.
| #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) |
Bit 3
Definition at line 10274 of file stm32f4xx.h.
| #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) |
Bit 4
Definition at line 10275 of file stm32f4xx.h.
| #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) |
Bit 5
Definition at line 10276 of file stm32f4xx.h.
| #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) |
Muate value
Definition at line 10268 of file stm32f4xx.h.
| #define SAI_xCR2_TRIS ((uint32_t)0x00000010) |
TRIState Management on data line
Definition at line 10266 of file stm32f4xx.h.
| #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF) |
Definition at line 10363 of file stm32f4xx.h.
| #define SAI_xFRCR_FRL ((uint32_t)0x000000FF) |
FRL[1:0](Frame length)
Definition at line 10285 of file stm32f4xx.h.
| #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 10286 of file stm32f4xx.h.
| #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 10287 of file stm32f4xx.h.
| #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 10288 of file stm32f4xx.h.
| #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 10289 of file stm32f4xx.h.
| #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 10290 of file stm32f4xx.h.
| #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) |
Bit 5
Definition at line 10291 of file stm32f4xx.h.
| #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) |
Bit 6
Definition at line 10292 of file stm32f4xx.h.
| #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) |
Bit 7
Definition at line 10293 of file stm32f4xx.h.
| #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) |
FRL[1:0] (Frame synchronization active level length)
Definition at line 10295 of file stm32f4xx.h.
| #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 10296 of file stm32f4xx.h.
| #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 10297 of file stm32f4xx.h.
| #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 10298 of file stm32f4xx.h.
| #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 10299 of file stm32f4xx.h.
| #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) |
Bit 4
Definition at line 10300 of file stm32f4xx.h.
| #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) |
Bit 5
Definition at line 10301 of file stm32f4xx.h.
| #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) |
Bit 6
Definition at line 10302 of file stm32f4xx.h.
| #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) |
Frame Synchronization Definition
Definition at line 10304 of file stm32f4xx.h.
| #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) |
Frame Synchronization OFFset
Definition at line 10306 of file stm32f4xx.h.
| #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL |
Definition at line 10308 of file stm32f4xx.h.
| #define SAI_xFRCR_FSPOL ((uint32_t)0x00020000) |
Frame Synchronization POLarity
Definition at line 10305 of file stm32f4xx.h.
| #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) |
Anticipated frame synchronization detection interrupt enable
Definition at line 10336 of file stm32f4xx.h.
| #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) |
Codec not ready interrupt enable
Definition at line 10335 of file stm32f4xx.h.
| #define SAI_xIMR_FREQIE ((uint32_t)0x00000008) |
FIFO request interrupt enable
Definition at line 10334 of file stm32f4xx.h.
| #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) |
Late frame synchronization detection interrupt enable
Definition at line 10337 of file stm32f4xx.h.
| #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) |
Mute detection interrupt enable
Definition at line 10332 of file stm32f4xx.h.
| #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) |
Overrun underrun interrupt enable
Definition at line 10331 of file stm32f4xx.h.
| #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) |
Wrong Clock Configuration interrupt enable
Definition at line 10333 of file stm32f4xx.h.
| #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) |
FRL[4:0](First Bit Offset)
Definition at line 10311 of file stm32f4xx.h.
| #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 10312 of file stm32f4xx.h.
| #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 10313 of file stm32f4xx.h.
| #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 10314 of file stm32f4xx.h.
| #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) |
Bit 3
Definition at line 10315 of file stm32f4xx.h.
| #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) |
Bit 4
Definition at line 10316 of file stm32f4xx.h.
| #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) |
NBSLOT[3:0] (Number of Slot in audio Frame)
Definition at line 10322 of file stm32f4xx.h.
| #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) |
Bit 0
Definition at line 10323 of file stm32f4xx.h.
| #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) |
Bit 1
Definition at line 10324 of file stm32f4xx.h.
| #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) |
Bit 2
Definition at line 10325 of file stm32f4xx.h.
| #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) |
Bit 3
Definition at line 10326 of file stm32f4xx.h.
| #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) |
SLOTEN[15:0] (Slot Enable)
Definition at line 10328 of file stm32f4xx.h.
| #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) |
SLOTSZ[1:0] (Slot size)
Definition at line 10318 of file stm32f4xx.h.
| #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) |
Bit 0
Definition at line 10319 of file stm32f4xx.h.
| #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) |
Bit 1
Definition at line 10320 of file stm32f4xx.h.
| #define SAI_xSR_AFSDET ((uint32_t)0x00000020) |
Anticipated frame synchronization detection
Definition at line 10345 of file stm32f4xx.h.
| #define SAI_xSR_CNRDY ((uint32_t)0x00000010) |
Codec not ready
Definition at line 10344 of file stm32f4xx.h.
| #define SAI_xSR_FLVL ((uint32_t)0x00070000) |
FLVL[2:0] (FIFO Level Threshold)
Definition at line 10348 of file stm32f4xx.h.
| #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) |
Bit 0
Definition at line 10349 of file stm32f4xx.h.
| #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) |
Bit 1
Definition at line 10350 of file stm32f4xx.h.
| #define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) |
Bit 2
Definition at line 10351 of file stm32f4xx.h.
| #define SAI_xSR_FREQ ((uint32_t)0x00000008) |
FIFO request
Definition at line 10343 of file stm32f4xx.h.
| #define SAI_xSR_LFSDET ((uint32_t)0x00000040) |
Late frame synchronization detection
Definition at line 10346 of file stm32f4xx.h.
| #define SAI_xSR_MUTEDET ((uint32_t)0x00000002) |
Mute detection
Definition at line 10341 of file stm32f4xx.h.
| #define SAI_xSR_OVRUDR ((uint32_t)0x00000001) |
Overrun underrun
Definition at line 10340 of file stm32f4xx.h.
| #define SAI_xSR_WCKCFG ((uint32_t)0x00000004) |
Wrong Clock Configuration
Definition at line 10342 of file stm32f4xx.h.
| #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
Command argument
Definition at line 10467 of file stm32f4xx.h.
| #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) |
Clock divider bypass enable bit
Definition at line 10457 of file stm32f4xx.h.
| #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) |
Clock divide factor
Definition at line 10454 of file stm32f4xx.h.
| #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) |
Clock enable bit
Definition at line 10455 of file stm32f4xx.h.
| #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) |
HW Flow Control enable
Definition at line 10464 of file stm32f4xx.h.
| #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) |
SDIO_CK dephasing selection bit
Definition at line 10463 of file stm32f4xx.h.
| #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) |
Power saving configuration bit
Definition at line 10456 of file stm32f4xx.h.
| #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) |
WIDBUS[1:0] bits (Wide bus mode enable bit)
Definition at line 10459 of file stm32f4xx.h.
| #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) |
Bit 0
Definition at line 10460 of file stm32f4xx.h.
| #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) |
Bit 1
Definition at line 10461 of file stm32f4xx.h.
| #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) |
CE-ATA command
Definition at line 10482 of file stm32f4xx.h.
| #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) |
Command Index
Definition at line 10470 of file stm32f4xx.h.
| #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) |
Command path state machine (CPSM) Enable bit
Definition at line 10478 of file stm32f4xx.h.
| #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) |
Enable CMD completion
Definition at line 10480 of file stm32f4xx.h.
| #define SDIO_CMD_NIEN ((uint16_t)0x2000) |
Not Interrupt Enable
Definition at line 10481 of file stm32f4xx.h.
| #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) |
SD I/O suspend command
Definition at line 10479 of file stm32f4xx.h.
| #define SDIO_CMD_WAITINT ((uint16_t)0x0100) |
CPSM Waits for Interrupt Request
Definition at line 10476 of file stm32f4xx.h.
| #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) |
CPSM Waits for ends of data transfer (CmdPend internal signal)
Definition at line 10477 of file stm32f4xx.h.
| #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) |
WAITRESP[1:0] bits (Wait for response bits)
Definition at line 10472 of file stm32f4xx.h.
| #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) |
Bit 0
Definition at line 10473 of file stm32f4xx.h.
| #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) |
Bit 1
Definition at line 10474 of file stm32f4xx.h.
| #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
Data count value
Definition at line 10526 of file stm32f4xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) |
DBLOCKSIZE[3:0] bits (Data block size)
Definition at line 10514 of file stm32f4xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 10515 of file stm32f4xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 10516 of file stm32f4xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) |
Bit 2
Definition at line 10517 of file stm32f4xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) |
Bit 3
Definition at line 10518 of file stm32f4xx.h.
| #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) |
DMA enabled bit
Definition at line 10512 of file stm32f4xx.h.
| #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) |
Data transfer direction selection
Definition at line 10510 of file stm32f4xx.h.
| #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) |
Data transfer enabled bit
Definition at line 10509 of file stm32f4xx.h.
| #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) |
Data transfer mode selection
Definition at line 10511 of file stm32f4xx.h.
| #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) |
Read wait mode
Definition at line 10522 of file stm32f4xx.h.
| #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) |
Read wait start
Definition at line 10520 of file stm32f4xx.h.
| #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) |
Read wait stop
Definition at line 10521 of file stm32f4xx.h.
| #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) |
SD I/O enable functions
Definition at line 10523 of file stm32f4xx.h.
| #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
Data length value
Definition at line 10506 of file stm32f4xx.h.
| #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
Data timeout period.
Definition at line 10503 of file stm32f4xx.h.
| #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
Receive and transmit FIFO data
Definition at line 10599 of file stm32f4xx.h.
| #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
Remaining number of words to be written to or read from the FIFO
Definition at line 10596 of file stm32f4xx.h.
| #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
CCRCFAIL flag clear bit
Definition at line 10555 of file stm32f4xx.h.
| #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
CEATAEND flag clear bit
Definition at line 10567 of file stm32f4xx.h.
| #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
CMDREND flag clear bit
Definition at line 10561 of file stm32f4xx.h.
| #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
CMDSENT flag clear bit
Definition at line 10562 of file stm32f4xx.h.
| #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
CTIMEOUT flag clear bit
Definition at line 10557 of file stm32f4xx.h.
| #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
DATAEND flag clear bit
Definition at line 10563 of file stm32f4xx.h.
| #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
DBCKEND flag clear bit
Definition at line 10565 of file stm32f4xx.h.
| #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
DCRCFAIL flag clear bit
Definition at line 10556 of file stm32f4xx.h.
| #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
DTIMEOUT flag clear bit
Definition at line 10558 of file stm32f4xx.h.
| #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
RXOVERR flag clear bit
Definition at line 10560 of file stm32f4xx.h.
| #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
SDIOIT flag clear bit
Definition at line 10566 of file stm32f4xx.h.
| #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
STBITERR flag clear bit
Definition at line 10564 of file stm32f4xx.h.
| #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
TXUNDERR flag clear bit
Definition at line 10559 of file stm32f4xx.h.
| #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
Command CRC Fail Interrupt Enable
Definition at line 10570 of file stm32f4xx.h.
| #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
CE-ATA command completion signal received Interrupt Enable
Definition at line 10593 of file stm32f4xx.h.
| #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
CCommand Acting Interrupt Enable
Definition at line 10581 of file stm32f4xx.h.
| #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
Command Response Received Interrupt Enable
Definition at line 10576 of file stm32f4xx.h.
| #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
Command Sent Interrupt Enable
Definition at line 10577 of file stm32f4xx.h.
| #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
Command TimeOut Interrupt Enable
Definition at line 10572 of file stm32f4xx.h.
| #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
Data End Interrupt Enable
Definition at line 10578 of file stm32f4xx.h.
| #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
Data Block End Interrupt Enable
Definition at line 10580 of file stm32f4xx.h.
| #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
Data CRC Fail Interrupt Enable
Definition at line 10571 of file stm32f4xx.h.
| #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
Data TimeOut Interrupt Enable
Definition at line 10573 of file stm32f4xx.h.
| #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
Data receive acting interrupt enabled
Definition at line 10583 of file stm32f4xx.h.
| #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
Data available in Rx FIFO interrupt Enable
Definition at line 10591 of file stm32f4xx.h.
| #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
Rx FIFO Empty interrupt Enable
Definition at line 10589 of file stm32f4xx.h.
| #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
Rx FIFO Full interrupt Enable
Definition at line 10587 of file stm32f4xx.h.
| #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
Rx FIFO Half Full interrupt Enable
Definition at line 10585 of file stm32f4xx.h.
| #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
Rx FIFO OverRun Error Interrupt Enable
Definition at line 10575 of file stm32f4xx.h.
| #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
SDIO Mode Interrupt Received interrupt Enable
Definition at line 10592 of file stm32f4xx.h.
| #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
Start Bit Error Interrupt Enable
Definition at line 10579 of file stm32f4xx.h.
| #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
Data Transmit Acting Interrupt Enable
Definition at line 10582 of file stm32f4xx.h.
| #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
Data available in Tx FIFO interrupt Enable
Definition at line 10590 of file stm32f4xx.h.
| #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
Tx FIFO Empty interrupt Enable
Definition at line 10588 of file stm32f4xx.h.
| #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
Tx FIFO Full interrupt Enable
Definition at line 10586 of file stm32f4xx.h.
| #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
Tx FIFO Half Empty interrupt Enable
Definition at line 10584 of file stm32f4xx.h.
| #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
Tx FIFO UnderRun Error Interrupt Enable
Definition at line 10574 of file stm32f4xx.h.
| #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) |
PWRCTRL[1:0] bits (Power supply control bits)
Definition at line 10449 of file stm32f4xx.h.
| #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) |
Bit 0
Definition at line 10450 of file stm32f4xx.h.
| #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) |
Bit 1
Definition at line 10451 of file stm32f4xx.h.
| #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
Card Status
Definition at line 10488 of file stm32f4xx.h.
| #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
Card Status
Definition at line 10491 of file stm32f4xx.h.
| #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
Card Status
Definition at line 10494 of file stm32f4xx.h.
| #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
Card Status
Definition at line 10497 of file stm32f4xx.h.
| #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
Card Status
Definition at line 10500 of file stm32f4xx.h.
| #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) |
Response command index
Definition at line 10485 of file stm32f4xx.h.
| #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
Command response received (CRC check failed)
Definition at line 10529 of file stm32f4xx.h.
| #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
CE-ATA command completion signal received for CMD61
Definition at line 10552 of file stm32f4xx.h.
| #define SDIO_STA_CMDACT ((uint32_t)0x00000800) |
Command transfer in progress
Definition at line 10540 of file stm32f4xx.h.
| #define SDIO_STA_CMDREND ((uint32_t)0x00000040) |
Command response received (CRC check passed)
Definition at line 10535 of file stm32f4xx.h.
| #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
Command sent (no response required)
Definition at line 10536 of file stm32f4xx.h.
| #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
Command response timeout
Definition at line 10531 of file stm32f4xx.h.
| #define SDIO_STA_DATAEND ((uint32_t)0x00000100) |
Data end (data counter, SDIDCOUNT, is zero)
Definition at line 10537 of file stm32f4xx.h.
| #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
Data block sent/received (CRC check passed)
Definition at line 10539 of file stm32f4xx.h.
| #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
Data block sent/received (CRC check failed)
Definition at line 10530 of file stm32f4xx.h.
| #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
Data timeout
Definition at line 10532 of file stm32f4xx.h.
| #define SDIO_STA_RXACT ((uint32_t)0x00002000) |
Data receive in progress
Definition at line 10542 of file stm32f4xx.h.
| #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
Data available in receive FIFO
Definition at line 10550 of file stm32f4xx.h.
| #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
Receive FIFO empty
Definition at line 10548 of file stm32f4xx.h.
| #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
Receive FIFO full
Definition at line 10546 of file stm32f4xx.h.
| #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
Receive FIFO Half Full: there are at least 8 words in the FIFO
Definition at line 10544 of file stm32f4xx.h.
| #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
Received FIFO overrun error
Definition at line 10534 of file stm32f4xx.h.
| #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
SDIO interrupt received
Definition at line 10551 of file stm32f4xx.h.
| #define SDIO_STA_STBITERR ((uint32_t)0x00000200) |
Start bit not detected on all data signals in wide bus mode
Definition at line 10538 of file stm32f4xx.h.
| #define SDIO_STA_TXACT ((uint32_t)0x00001000) |
Data transmit in progress
Definition at line 10541 of file stm32f4xx.h.
| #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
Data available in transmit FIFO
Definition at line 10549 of file stm32f4xx.h.
| #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
Transmit FIFO empty
Definition at line 10547 of file stm32f4xx.h.
| #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
Transmit FIFO full
Definition at line 10545 of file stm32f4xx.h.
| #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
Transmit FIFO Half Empty: at least 8 words can be written into the FIFO
Definition at line 10543 of file stm32f4xx.h.
| #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
Transmit FIFO underrun error
Definition at line 10533 of file stm32f4xx.h.
| #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) |
Bidirectional data mode enable
Definition at line 10625 of file stm32f4xx.h.
| #define SPI_CR1_BIDIOE ((uint16_t)0x4000) |
Output enable in bidirectional mode
Definition at line 10624 of file stm32f4xx.h.
| #define SPI_CR1_BR ((uint16_t)0x0038) |
BR[2:0] bits (Baud Rate Control)
Definition at line 10611 of file stm32f4xx.h.
| #define SPI_CR1_BR_0 ((uint16_t)0x0008) |
Bit 0
Definition at line 10612 of file stm32f4xx.h.
| #define SPI_CR1_BR_1 ((uint16_t)0x0010) |
Bit 1
Definition at line 10613 of file stm32f4xx.h.
| #define SPI_CR1_BR_2 ((uint16_t)0x0020) |
Bit 2
Definition at line 10614 of file stm32f4xx.h.
| #define SPI_CR1_CPHA ((uint16_t)0x0001) |
Clock Phase
Definition at line 10607 of file stm32f4xx.h.
| #define SPI_CR1_CPOL ((uint16_t)0x0002) |
Clock Polarity
Definition at line 10608 of file stm32f4xx.h.
| #define SPI_CR1_CRCEN ((uint16_t)0x2000) |
Hardware CRC calculation enable
Definition at line 10623 of file stm32f4xx.h.
Referenced by SPI_CalculateCRC().
| #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) |
| #define SPI_CR1_DFF ((uint16_t)0x0800) |
Data Frame Format
Definition at line 10621 of file stm32f4xx.h.
| #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) |
Frame Format
Definition at line 10617 of file stm32f4xx.h.
| #define SPI_CR1_MSTR ((uint16_t)0x0004) |
Master Selection
Definition at line 10609 of file stm32f4xx.h.
| #define SPI_CR1_RXONLY ((uint16_t)0x0400) |
Receive only
Definition at line 10620 of file stm32f4xx.h.
| #define SPI_CR1_SPE ((uint16_t)0x0040) |
| #define SPI_CR1_SSI ((uint16_t)0x0100) |
Internal slave select
Definition at line 10618 of file stm32f4xx.h.
| #define SPI_CR1_SSM ((uint16_t)0x0200) |
Software slave management
Definition at line 10619 of file stm32f4xx.h.
| #define SPI_CR2_ERRIE ((uint8_t)0x20) |
Error Interrupt Enable
Definition at line 10631 of file stm32f4xx.h.
| #define SPI_CR2_RXDMAEN ((uint8_t)0x01) |
Rx Buffer DMA Enable
Definition at line 10628 of file stm32f4xx.h.
| #define SPI_CR2_RXNEIE ((uint8_t)0x40) |
RX buffer Not Empty Interrupt Enable
Definition at line 10632 of file stm32f4xx.h.
| #define SPI_CR2_SSOE ((uint8_t)0x04) |
| #define SPI_CR2_TXDMAEN ((uint8_t)0x02) |
Tx Buffer DMA Enable
Definition at line 10629 of file stm32f4xx.h.
| #define SPI_CR2_TXEIE ((uint8_t)0x80) |
Tx buffer Empty Interrupt Enable
Definition at line 10633 of file stm32f4xx.h.
| #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) |
CRC polynomial register
Definition at line 10649 of file stm32f4xx.h.
| #define SPI_DR_DR ((uint16_t)0xFFFF) |
Data Register
Definition at line 10646 of file stm32f4xx.h.
| #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) |
Channel length (number of bits per audio channel)
Definition at line 10658 of file stm32f4xx.h.
| #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) |
steady state clock polarity
Definition at line 10664 of file stm32f4xx.h.
| #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) |
DATLEN[1:0] bits (Data length to be transferred)
Definition at line 10660 of file stm32f4xx.h.
| #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) |
Bit 0
Definition at line 10661 of file stm32f4xx.h.
| #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) |
Bit 1
Definition at line 10662 of file stm32f4xx.h.
| #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) |
I2SCFG[1:0] bits (I2S configuration mode)
Definition at line 10672 of file stm32f4xx.h.
| #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) |
Bit 0
Definition at line 10673 of file stm32f4xx.h.
| #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) |
Bit 1
Definition at line 10674 of file stm32f4xx.h.
| #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) |
| #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) |
I2S mode selection
Definition at line 10677 of file stm32f4xx.h.
Referenced by I2S_FullDuplexConfig(), I2S_Init(), and SPI_Init().
| #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) |
I2SSTD[1:0] bits (I2S standard selection)
Definition at line 10666 of file stm32f4xx.h.
| #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 10667 of file stm32f4xx.h.
| #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 10668 of file stm32f4xx.h.
| #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) |
PCM frame synchronization
Definition at line 10670 of file stm32f4xx.h.
| #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) |
I2S Linear prescaler
Definition at line 10683 of file stm32f4xx.h.
| #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) |
Master Clock Output Enable
Definition at line 10685 of file stm32f4xx.h.
| #define SPI_I2SPR_ODD ((uint16_t)0x0100) |
Odd factor for the prescaler
Definition at line 10684 of file stm32f4xx.h.
| #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) |
Rx CRC Register
Definition at line 10652 of file stm32f4xx.h.
| #define SPI_SR_BSY ((uint8_t)0x80) |
Busy flag
Definition at line 10643 of file stm32f4xx.h.
| #define SPI_SR_CHSIDE ((uint8_t)0x04) |
Channel side
Definition at line 10638 of file stm32f4xx.h.
| #define SPI_SR_CRCERR ((uint8_t)0x10) |
CRC Error flag
Definition at line 10640 of file stm32f4xx.h.
| #define SPI_SR_MODF ((uint8_t)0x20) |
Mode fault
Definition at line 10641 of file stm32f4xx.h.
| #define SPI_SR_OVR ((uint8_t)0x40) |
Overrun flag
Definition at line 10642 of file stm32f4xx.h.
| #define SPI_SR_RXNE ((uint8_t)0x01) |
Receive buffer Not Empty
Definition at line 10636 of file stm32f4xx.h.
| #define SPI_SR_TXE ((uint8_t)0x02) |
Transmit buffer Empty
Definition at line 10637 of file stm32f4xx.h.
| #define SPI_SR_UDR ((uint8_t)0x08) |
Underrun flag
Definition at line 10639 of file stm32f4xx.h.
| #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) |
Tx CRC Register
Definition at line 10655 of file stm32f4xx.h.
| #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) |
Compensation cell ready flag
Definition at line 10980 of file stm32f4xx.h.
| #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) |
Compensation cell power-down
Definition at line 10981 of file stm32f4xx.h.
Referenced by SYSCFG_GetCompensationCellStatus().
| #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) |
EXTI 0 configuration
Definition at line 10716 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) |
PB[0] pin
Definition at line 10724 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) |
PC[0] pin
Definition at line 10725 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) |
PD[0] pin
Definition at line 10726 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) |
PE[0] pin
Definition at line 10727 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) |
PF[0] pin
Definition at line 10728 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) |
PG[0] pin
Definition at line 10729 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) |
PH[0] pin
Definition at line 10730 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) |
PI[0] pin
Definition at line 10731 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PJ ((uint16_t)0x0009) |
PJ[0] pin
Definition at line 10732 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PK ((uint16_t)0x000A) |
PK[0] pin
Definition at line 10733 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) |
EXTI 1 configuration
Definition at line 10717 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) |
PB[1] pin
Definition at line 10739 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) |
PC[1] pin
Definition at line 10740 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) |
PD[1] pin
Definition at line 10741 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) |
PE[1] pin
Definition at line 10742 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) |
PF[1] pin
Definition at line 10743 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) |
PG[1] pin
Definition at line 10744 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) |
PH[1] pin
Definition at line 10745 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) |
PI[1] pin
Definition at line 10746 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PJ ((uint16_t)0x0090) |
PJ[1] pin
Definition at line 10747 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PK ((uint16_t)0x00A0) |
PK[1] pin
Definition at line 10748 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) |
EXTI 2 configuration
Definition at line 10718 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) |
PB[2] pin
Definition at line 10754 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) |
PC[2] pin
Definition at line 10755 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) |
PD[2] pin
Definition at line 10756 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) |
PE[2] pin
Definition at line 10757 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) |
PF[2] pin
Definition at line 10758 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) |
PG[2] pin
Definition at line 10759 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) |
PH[2] pin
Definition at line 10760 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) |
PI[2] pin
Definition at line 10761 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PJ ((uint16_t)0x0900) |
PJ[2] pin
Definition at line 10762 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PK ((uint16_t)0x0A00) |
PK[2] pin
Definition at line 10763 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) |
EXTI 3 configuration
Definition at line 10719 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) |
PB[3] pin
Definition at line 10769 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) |
PC[3] pin
Definition at line 10770 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) |
PD[3] pin
Definition at line 10771 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) |
PE[3] pin
Definition at line 10772 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) |
PF[3] pin
Definition at line 10773 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) |
PG[3] pin
Definition at line 10774 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) |
PH[3] pin
Definition at line 10775 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) |
PI[3] pin
Definition at line 10776 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PJ ((uint16_t)0x9000) |
PJ[3] pin
Definition at line 10777 of file stm32f4xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PK ((uint16_t)0xA000) |
PK[3] pin
Definition at line 10778 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) |
EXTI 4 configuration
Definition at line 10781 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) |
PB[4] pin
Definition at line 10789 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) |
PC[4] pin
Definition at line 10790 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) |
PD[4] pin
Definition at line 10791 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) |
PE[4] pin
Definition at line 10792 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) |
PF[4] pin
Definition at line 10793 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) |
PG[4] pin
Definition at line 10794 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) |
PH[4] pin
Definition at line 10795 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) |
PI[4] pin
Definition at line 10796 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PJ ((uint16_t)0x0009) |
PJ[4] pin
Definition at line 10797 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PK ((uint16_t)0x000A) |
PK[4] pin
Definition at line 10798 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) |
EXTI 5 configuration
Definition at line 10782 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) |
PB[5] pin
Definition at line 10804 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) |
PC[5] pin
Definition at line 10805 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) |
PD[5] pin
Definition at line 10806 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) |
PE[5] pin
Definition at line 10807 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) |
PF[5] pin
Definition at line 10808 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) |
PG[5] pin
Definition at line 10809 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) |
PH[5] pin
Definition at line 10810 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) |
PI[5] pin
Definition at line 10811 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PJ ((uint16_t)0x0090) |
PJ[5] pin
Definition at line 10812 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PK ((uint16_t)0x00A0) |
PK[5] pin
Definition at line 10813 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) |
EXTI 6 configuration
Definition at line 10783 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) |
PB[6] pin
Definition at line 10819 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) |
PC[6] pin
Definition at line 10820 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) |
PD[6] pin
Definition at line 10821 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) |
PE[6] pin
Definition at line 10822 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) |
PF[6] pin
Definition at line 10823 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) |
PG[6] pin
Definition at line 10824 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) |
PH[6] pin
Definition at line 10825 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) |
PI[6] pin
Definition at line 10826 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PJ ((uint16_t)0x0900) |
PJ[6] pin
Definition at line 10827 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PK ((uint16_t)0x0A00) |
PK[6] pin
Definition at line 10828 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) |
EXTI 7 configuration
Definition at line 10784 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) |
PB[7] pin
Definition at line 10834 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) |
PC[7] pin
Definition at line 10835 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) |
PD[7] pin
Definition at line 10836 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) |
PE[7] pin
Definition at line 10837 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) |
PF[7] pin
Definition at line 10838 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) |
PG[7] pin
Definition at line 10839 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) |
PH[7] pin
Definition at line 10840 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) |
PI[7] pin
Definition at line 10841 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PJ ((uint16_t)0x9000) |
PJ[7] pin
Definition at line 10842 of file stm32f4xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PK ((uint16_t)0xA000) |
PK[7] pin
Definition at line 10843 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) |
EXTI 10 configuration
Definition at line 10848 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) |
PB[10] pin
Definition at line 10883 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) |
PC[10] pin
Definition at line 10884 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) |
PD[10] pin
Definition at line 10885 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) |
PE[10] pin
Definition at line 10886 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) |
PF[10] pin
Definition at line 10887 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) |
PG[10] pin
Definition at line 10888 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) |
PH[10] pin
Definition at line 10889 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) |
PI[10] pin
Definition at line 10890 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PJ ((uint16_t)0x0900) |
PJ[10] pin
Definition at line 10891 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) |
EXTI 11 configuration
Definition at line 10849 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) |
PB[11] pin
Definition at line 10897 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) |
PC[11] pin
Definition at line 10898 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) |
PD[11] pin
Definition at line 10899 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) |
PE[11] pin
Definition at line 10900 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) |
PF[11] pin
Definition at line 10901 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) |
PG[11] pin
Definition at line 10902 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) |
PH[11] pin
Definition at line 10903 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) |
PI[11] pin
Definition at line 10904 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PJ ((uint16_t)0x9000) |
PJ[11] pin
Definition at line 10905 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) |
EXTI 8 configuration
Definition at line 10846 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) |
PB[8] pin
Definition at line 10855 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) |
PC[8] pin
Definition at line 10856 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) |
PD[8] pin
Definition at line 10857 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) |
PE[8] pin
Definition at line 10858 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) |
PF[8] pin
Definition at line 10859 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) |
PG[8] pin
Definition at line 10860 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) |
PH[8] pin
Definition at line 10861 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) |
PI[8] pin
Definition at line 10862 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PJ ((uint16_t)0x0009) |
PJ[8] pin
Definition at line 10863 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) |
EXTI 9 configuration
Definition at line 10847 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) |
PB[9] pin
Definition at line 10869 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) |
PC[9] pin
Definition at line 10870 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) |
PD[9] pin
Definition at line 10871 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) |
PE[9] pin
Definition at line 10872 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) |
PF[9] pin
Definition at line 10873 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) |
PG[9] pin
Definition at line 10874 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) |
PH[9] pin
Definition at line 10875 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) |
PI[9] pin
Definition at line 10876 of file stm32f4xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PJ ((uint16_t)0x0090) |
PJ[9] pin
Definition at line 10877 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) |
EXTI 12 configuration
Definition at line 10908 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) |
PB[12] pin
Definition at line 10916 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) |
PC[12] pin
Definition at line 10917 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) |
PD[12] pin
Definition at line 10918 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) |
PE[12] pin
Definition at line 10919 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) |
PF[12] pin
Definition at line 10920 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) |
PG[12] pin
Definition at line 10921 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007) |
PH[12] pin
Definition at line 10922 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PI ((uint16_t)0x0008) |
PI[12] pin
Definition at line 10923 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PJ ((uint16_t)0x0009) |
PJ[12] pin
Definition at line 10924 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) |
EXTI 13 configuration
Definition at line 10909 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) |
PB[13] pin
Definition at line 10930 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) |
PC[13] pin
Definition at line 10931 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) |
PD[13] pin
Definition at line 10932 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) |
PE[13] pin
Definition at line 10933 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) |
PF[13] pin
Definition at line 10934 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) |
PG[13] pin
Definition at line 10935 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070) |
PH[13] pin
Definition at line 10936 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PI ((uint16_t)0x0008) |
PI[13] pin
Definition at line 10937 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PJ ((uint16_t)0x0009) |
PJ[13] pin
Definition at line 10938 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) |
EXTI 14 configuration
Definition at line 10910 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) |
PB[14] pin
Definition at line 10944 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) |
PC[14] pin
Definition at line 10945 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) |
PD[14] pin
Definition at line 10946 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) |
PE[14] pin
Definition at line 10947 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) |
PF[14] pin
Definition at line 10948 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) |
PG[14] pin
Definition at line 10949 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700) |
PH[14] pin
Definition at line 10950 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PI ((uint16_t)0x0800) |
PI[14] pin
Definition at line 10951 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PJ ((uint16_t)0x0900) |
PJ[14] pin
Definition at line 10952 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) |
EXTI 15 configuration
Definition at line 10911 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) |
| #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) |
PB[15] pin
Definition at line 10958 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) |
PC[15] pin
Definition at line 10959 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) |
PD[15] pin
Definition at line 10960 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) |
PE[15] pin
Definition at line 10961 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) |
PF[15] pin
Definition at line 10962 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) |
PG[15] pin
Definition at line 10963 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000) |
PH[15] pin
Definition at line 10964 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PI ((uint16_t)0x8000) |
PI[15] pin
Definition at line 10965 of file stm32f4xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PJ ((uint16_t)0x9000) |
PJ[15] pin
Definition at line 10966 of file stm32f4xx.h.
| #define SYSCFG_MEMRMP_FB_MODE ((uint32_t)0x00000100) |
User Flash Bank mode
Definition at line 10698 of file stm32f4xx.h.
| #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) |
SYSCFG_Memory Remap Config
Definition at line 10693 of file stm32f4xx.h.
| #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) |
Bit 0
Definition at line 10694 of file stm32f4xx.h.
| #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) |
Bit 1
Definition at line 10695 of file stm32f4xx.h.
| #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004) |
Bit 2
Definition at line 10696 of file stm32f4xx.h.
| #define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) |
FMC memory mapping swap
Definition at line 10700 of file stm32f4xx.h.
| #define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400) |
Bit 0
Definition at line 10701 of file stm32f4xx.h.
| #define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800) |
Bit 1
Definition at line 10702 of file stm32f4xx.h.
| #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) |
Refer to AN4073 on how to use this bit
Definition at line 10707 of file stm32f4xx.h.
| #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) |
Refer to AN4073 on how to use this bit
Definition at line 10708 of file stm32f4xx.h.
| #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) |
Refer to AN4073 on how to use this bit
Definition at line 10709 of file stm32f4xx.h.
| #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) |
Refer to AN4073 on how to use this bit
Definition at line 10706 of file stm32f4xx.h.
| #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL |
Definition at line 10713 of file stm32f4xx.h.
| #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) |
Ethernet PHY interface selection
Definition at line 10711 of file stm32f4xx.h.
| #define TIM_ARR_ARR ((uint16_t)0xFFFF) |
actual auto-reload Value
Definition at line 11240 of file stm32f4xx.h.
| #define TIM_BDTR_AOE ((uint16_t)0x4000) |
Automatic Output enable
Definition at line 11276 of file stm32f4xx.h.
| #define TIM_BDTR_BKE ((uint16_t)0x1000) |
Break enable
Definition at line 11274 of file stm32f4xx.h.
| #define TIM_BDTR_BKP ((uint16_t)0x2000) |
Break Polarity
Definition at line 11275 of file stm32f4xx.h.
| #define TIM_BDTR_DTG ((uint16_t)0x00FF) |
DTG[0:7] bits (Dead-Time Generator set-up)
Definition at line 11258 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) |
Bit 0
Definition at line 11259 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 11260 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) |
Bit 2
Definition at line 11261 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) |
Bit 3
Definition at line 11262 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) |
Bit 4
Definition at line 11263 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) |
Bit 5
Definition at line 11264 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) |
Bit 6
Definition at line 11265 of file stm32f4xx.h.
| #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) |
Bit 7
Definition at line 11266 of file stm32f4xx.h.
| #define TIM_BDTR_LOCK ((uint16_t)0x0300) |
LOCK[1:0] bits (Lock Configuration)
Definition at line 11268 of file stm32f4xx.h.
| #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) |
Bit 0
Definition at line 11269 of file stm32f4xx.h.
| #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) |
Bit 1
Definition at line 11270 of file stm32f4xx.h.
| #define TIM_BDTR_MOE ((uint16_t)0x8000) |
Main Output enable
Definition at line 11277 of file stm32f4xx.h.
Referenced by TIM_CtrlPWMOutputs().
| #define TIM_BDTR_OSSI ((uint16_t)0x0400) |
Off-State Selection for Idle mode
Definition at line 11272 of file stm32f4xx.h.
| #define TIM_BDTR_OSSR ((uint16_t)0x0800) |
Off-State Selection for Run mode
Definition at line 11273 of file stm32f4xx.h.
| #define TIM_CCER_CC1E ((uint16_t)0x0001) |
Capture/Compare 1 output enable
Definition at line 11217 of file stm32f4xx.h.
Referenced by TI1_Config(), and TIM_OC1Init().
| #define TIM_CCER_CC1NE ((uint16_t)0x0004) |
Capture/Compare 1 Complementary output enable
Definition at line 11219 of file stm32f4xx.h.
Referenced by TIM_OC1Init().
| #define TIM_CCER_CC1NP ((uint16_t)0x0008) |
Capture/Compare 1 Complementary output Polarity
Definition at line 11220 of file stm32f4xx.h.
Referenced by TI1_Config(), TIM_OC1Init(), and TIM_OC1NPolarityConfig().
| #define TIM_CCER_CC1P ((uint16_t)0x0002) |
Capture/Compare 1 output Polarity
Definition at line 11218 of file stm32f4xx.h.
Referenced by TI1_Config(), TIM_OC1Init(), and TIM_OC1PolarityConfig().
| #define TIM_CCER_CC2E ((uint16_t)0x0010) |
Capture/Compare 2 output enable
Definition at line 11221 of file stm32f4xx.h.
Referenced by TI2_Config(), and TIM_OC2Init().
| #define TIM_CCER_CC2NE ((uint16_t)0x0040) |
Capture/Compare 2 Complementary output enable
Definition at line 11223 of file stm32f4xx.h.
Referenced by TIM_OC2Init().
| #define TIM_CCER_CC2NP ((uint16_t)0x0080) |
Capture/Compare 2 Complementary output Polarity
Definition at line 11224 of file stm32f4xx.h.
Referenced by TI2_Config(), TIM_OC2Init(), and TIM_OC2NPolarityConfig().
| #define TIM_CCER_CC2P ((uint16_t)0x0020) |
Capture/Compare 2 output Polarity
Definition at line 11222 of file stm32f4xx.h.
Referenced by TI2_Config(), TIM_EncoderInterfaceConfig(), TIM_OC2Init(), and TIM_OC2PolarityConfig().
| #define TIM_CCER_CC3E ((uint16_t)0x0100) |
Capture/Compare 3 output enable
Definition at line 11225 of file stm32f4xx.h.
Referenced by TI3_Config(), and TIM_OC3Init().
| #define TIM_CCER_CC3NE ((uint16_t)0x0400) |
Capture/Compare 3 Complementary output enable
Definition at line 11227 of file stm32f4xx.h.
Referenced by TIM_OC3Init().
| #define TIM_CCER_CC3NP ((uint16_t)0x0800) |
Capture/Compare 3 Complementary output Polarity
Definition at line 11228 of file stm32f4xx.h.
Referenced by TI3_Config(), TIM_OC3Init(), and TIM_OC3NPolarityConfig().
| #define TIM_CCER_CC3P ((uint16_t)0x0200) |
Capture/Compare 3 output Polarity
Definition at line 11226 of file stm32f4xx.h.
Referenced by TI3_Config(), TIM_OC3Init(), and TIM_OC3PolarityConfig().
| #define TIM_CCER_CC4E ((uint16_t)0x1000) |
Capture/Compare 4 output enable
Definition at line 11229 of file stm32f4xx.h.
Referenced by TI4_Config(), and TIM_OC4Init().
| #define TIM_CCER_CC4NP ((uint16_t)0x8000) |
Capture/Compare 4 Complementary output Polarity
Definition at line 11231 of file stm32f4xx.h.
Referenced by TI4_Config().
| #define TIM_CCER_CC4P ((uint16_t)0x2000) |
Capture/Compare 4 output Polarity
Definition at line 11230 of file stm32f4xx.h.
Referenced by TI4_Config(), TIM_OC4Init(), and TIM_OC4PolarityConfig().
| #define TIM_CCMR1_CC1S ((uint16_t)0x0003) |
CC1S[1:0] bits (Capture/Compare 1 Selection)
Definition at line 11115 of file stm32f4xx.h.
Referenced by TIM_OC1Init().
| #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) |
| #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 11117 of file stm32f4xx.h.
| #define TIM_CCMR1_CC2S ((uint16_t)0x0300) |
CC2S[1:0] bits (Capture/Compare 2 Selection)
Definition at line 11129 of file stm32f4xx.h.
Referenced by TIM_EncoderInterfaceConfig(), and TIM_OC2Init().
| #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) |
| #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) |
Bit 1
Definition at line 11131 of file stm32f4xx.h.
| #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) |
IC1F[3:0] bits (Input Capture 1 Filter)
Definition at line 11149 of file stm32f4xx.h.
Referenced by TI1_Config().
| #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 11150 of file stm32f4xx.h.
| #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 11151 of file stm32f4xx.h.
| #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) |
Bit 2
Definition at line 11152 of file stm32f4xx.h.
| #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) |
Bit 3
Definition at line 11153 of file stm32f4xx.h.
| #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) |
IC1PSC[1:0] bits (Input Capture 1 Prescaler)
Definition at line 11145 of file stm32f4xx.h.
Referenced by TIM_SetIC1Prescaler().
| #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) |
Bit 0
Definition at line 11146 of file stm32f4xx.h.
| #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) |
Bit 1
Definition at line 11147 of file stm32f4xx.h.
| #define TIM_CCMR1_IC2F ((uint16_t)0xF000) |
IC2F[3:0] bits (Input Capture 2 Filter)
Definition at line 11159 of file stm32f4xx.h.
Referenced by TI2_Config(), and TI4_Config().
| #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) |
Bit 0
Definition at line 11160 of file stm32f4xx.h.
| #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) |
Bit 1
Definition at line 11161 of file stm32f4xx.h.
| #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) |
Bit 2
Definition at line 11162 of file stm32f4xx.h.
| #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) |
Bit 3
Definition at line 11163 of file stm32f4xx.h.
| #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) |
IC2PSC[1:0] bits (Input Capture 2 Prescaler)
Definition at line 11155 of file stm32f4xx.h.
Referenced by TIM_SetIC2Prescaler().
| #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) |
Bit 0
Definition at line 11156 of file stm32f4xx.h.
| #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) |
Bit 1
Definition at line 11157 of file stm32f4xx.h.
| #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) |
Output Compare 1Clear Enable
Definition at line 11127 of file stm32f4xx.h.
Referenced by TIM_ClearOC1Ref().
| #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) |
Output Compare 1 Fast enable
Definition at line 11119 of file stm32f4xx.h.
Referenced by TIM_OC1FastConfig().
| #define TIM_CCMR1_OC1M ((uint16_t)0x0070) |
OC1M[2:0] bits (Output Compare 1 Mode)
Definition at line 11122 of file stm32f4xx.h.
Referenced by TIM_ForcedOC1Config(), and TIM_OC1Init().
| #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 11123 of file stm32f4xx.h.
| #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 11124 of file stm32f4xx.h.
| #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) |
Bit 2
Definition at line 11125 of file stm32f4xx.h.
| #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) |
Output Compare 1 Preload enable
Definition at line 11120 of file stm32f4xx.h.
Referenced by TIM_OC1PreloadConfig().
| #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) |
Output Compare 2 Clear Enable
Definition at line 11141 of file stm32f4xx.h.
Referenced by TIM_ClearOC2Ref().
| #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) |
Output Compare 2 Fast enable
Definition at line 11133 of file stm32f4xx.h.
Referenced by TIM_OC2FastConfig().
| #define TIM_CCMR1_OC2M ((uint16_t)0x7000) |
OC2M[2:0] bits (Output Compare 2 Mode)
Definition at line 11136 of file stm32f4xx.h.
Referenced by TIM_ForcedOC2Config(), and TIM_OC2Init().
| #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) |
Bit 0
Definition at line 11137 of file stm32f4xx.h.
| #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) |
Bit 1
Definition at line 11138 of file stm32f4xx.h.
| #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) |
Bit 2
Definition at line 11139 of file stm32f4xx.h.
| #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) |
Output Compare 2 Preload enable
Definition at line 11134 of file stm32f4xx.h.
Referenced by TIM_OC2PreloadConfig().
| #define TIM_CCMR2_CC3S ((uint16_t)0x0003) |
CC3S[1:0] bits (Capture/Compare 3 Selection)
Definition at line 11166 of file stm32f4xx.h.
Referenced by TIM_OC3Init().
| #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) |
Bit 0
Definition at line 11167 of file stm32f4xx.h.
| #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 11168 of file stm32f4xx.h.
| #define TIM_CCMR2_CC4S ((uint16_t)0x0300) |
CC4S[1:0] bits (Capture/Compare 4 Selection)
Definition at line 11180 of file stm32f4xx.h.
Referenced by TIM_OC4Init().
| #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) |
Bit 0
Definition at line 11181 of file stm32f4xx.h.
| #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) |
Bit 1
Definition at line 11182 of file stm32f4xx.h.
| #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) |
IC3F[3:0] bits (Input Capture 3 Filter)
Definition at line 11200 of file stm32f4xx.h.
Referenced by TI3_Config().
| #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 11201 of file stm32f4xx.h.
| #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 11202 of file stm32f4xx.h.
| #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) |
Bit 2
Definition at line 11203 of file stm32f4xx.h.
| #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) |
Bit 3
Definition at line 11204 of file stm32f4xx.h.
| #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) |
IC3PSC[1:0] bits (Input Capture 3 Prescaler)
Definition at line 11196 of file stm32f4xx.h.
Referenced by TIM_SetIC3Prescaler().
| #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) |
Bit 0
Definition at line 11197 of file stm32f4xx.h.
| #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) |
Bit 1
Definition at line 11198 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4F ((uint16_t)0xF000) |
IC4F[3:0] bits (Input Capture 4 Filter)
Definition at line 11210 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) |
Bit 0
Definition at line 11211 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) |
Bit 1
Definition at line 11212 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) |
Bit 2
Definition at line 11213 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) |
Bit 3
Definition at line 11214 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) |
IC4PSC[1:0] bits (Input Capture 4 Prescaler)
Definition at line 11206 of file stm32f4xx.h.
Referenced by TIM_SetIC4Prescaler().
| #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) |
Bit 0
Definition at line 11207 of file stm32f4xx.h.
| #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) |
Bit 1
Definition at line 11208 of file stm32f4xx.h.
| #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) |
Output Compare 3 Clear Enable
Definition at line 11178 of file stm32f4xx.h.
Referenced by TIM_ClearOC3Ref().
| #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) |
Output Compare 3 Fast enable
Definition at line 11170 of file stm32f4xx.h.
Referenced by TIM_OC3FastConfig().
| #define TIM_CCMR2_OC3M ((uint16_t)0x0070) |
OC3M[2:0] bits (Output Compare 3 Mode)
Definition at line 11173 of file stm32f4xx.h.
Referenced by TIM_ForcedOC3Config(), and TIM_OC3Init().
| #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 11174 of file stm32f4xx.h.
| #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 11175 of file stm32f4xx.h.
| #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) |
Bit 2
Definition at line 11176 of file stm32f4xx.h.
| #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) |
Output Compare 3 Preload enable
Definition at line 11171 of file stm32f4xx.h.
Referenced by TIM_OC3PreloadConfig().
| #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) |
Output Compare 4 Clear Enable
Definition at line 11192 of file stm32f4xx.h.
Referenced by TIM_ClearOC4Ref().
| #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) |
Output Compare 4 Fast enable
Definition at line 11184 of file stm32f4xx.h.
Referenced by TIM_OC4FastConfig().
| #define TIM_CCMR2_OC4M ((uint16_t)0x7000) |
OC4M[2:0] bits (Output Compare 4 Mode)
Definition at line 11187 of file stm32f4xx.h.
Referenced by TIM_ForcedOC4Config(), and TIM_OC4Init().
| #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) |
Bit 0
Definition at line 11188 of file stm32f4xx.h.
| #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) |
Bit 1
Definition at line 11189 of file stm32f4xx.h.
| #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) |
Bit 2
Definition at line 11190 of file stm32f4xx.h.
| #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) |
Output Compare 4 Preload enable
Definition at line 11185 of file stm32f4xx.h.
Referenced by TIM_OC4PreloadConfig().
| #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) |
Capture/Compare 1 Value
Definition at line 11246 of file stm32f4xx.h.
| #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) |
Capture/Compare 2 Value
Definition at line 11249 of file stm32f4xx.h.
| #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) |
Capture/Compare 3 Value
Definition at line 11252 of file stm32f4xx.h.
| #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) |
Capture/Compare 4 Value
Definition at line 11255 of file stm32f4xx.h.
| #define TIM_CNT_CNT ((uint16_t)0xFFFF) |
Counter Value
Definition at line 11234 of file stm32f4xx.h.
| #define TIM_CR1_ARPE ((uint16_t)0x0080) |
Auto-reload preload enable
Definition at line 11022 of file stm32f4xx.h.
Referenced by TIM_ARRPreloadConfig().
| #define TIM_CR1_CEN ((uint16_t)0x0001) |
| #define TIM_CR1_CKD ((uint16_t)0x0300) |
CKD[1:0] bits (clock division)
Definition at line 11024 of file stm32f4xx.h.
Referenced by TIM_SetClockDivision(), and TIM_TimeBaseInit().
| #define TIM_CR1_CKD_0 ((uint16_t)0x0100) |
Bit 0
Definition at line 11025 of file stm32f4xx.h.
| #define TIM_CR1_CKD_1 ((uint16_t)0x0200) |
Bit 1
Definition at line 11026 of file stm32f4xx.h.
| #define TIM_CR1_CMS ((uint16_t)0x0060) |
CMS[1:0] bits (Center-aligned mode selection)
Definition at line 11018 of file stm32f4xx.h.
Referenced by TIM_CounterModeConfig(), and TIM_TimeBaseInit().
| #define TIM_CR1_CMS_0 ((uint16_t)0x0020) |
Bit 0
Definition at line 11019 of file stm32f4xx.h.
| #define TIM_CR1_CMS_1 ((uint16_t)0x0040) |
Bit 1
Definition at line 11020 of file stm32f4xx.h.
| #define TIM_CR1_DIR ((uint16_t)0x0010) |
Direction
Definition at line 11016 of file stm32f4xx.h.
Referenced by TIM_CounterModeConfig(), and TIM_TimeBaseInit().
| #define TIM_CR1_OPM ((uint16_t)0x0008) |
One pulse mode
Definition at line 11015 of file stm32f4xx.h.
Referenced by TIM_SelectOnePulseMode().
| #define TIM_CR1_UDIS ((uint16_t)0x0002) |
Update disable
Definition at line 11013 of file stm32f4xx.h.
Referenced by TIM_UpdateDisableConfig().
| #define TIM_CR1_URS ((uint16_t)0x0004) |
Update request source
Definition at line 11014 of file stm32f4xx.h.
Referenced by TIM_UpdateRequestConfig().
| #define TIM_CR2_CCDS ((uint16_t)0x0008) |
Capture/Compare DMA Selection
Definition at line 11031 of file stm32f4xx.h.
Referenced by TIM_SelectCCDMA().
| #define TIM_CR2_CCPC ((uint16_t)0x0001) |
Capture/Compare Preloaded Control
Definition at line 11029 of file stm32f4xx.h.
Referenced by TIM_CCPreloadControl().
| #define TIM_CR2_CCUS ((uint16_t)0x0004) |
Capture/Compare Control Update Selection
Definition at line 11030 of file stm32f4xx.h.
Referenced by TIM_SelectCOM().
| #define TIM_CR2_MMS ((uint16_t)0x0070) |
MMS[2:0] bits (Master Mode Selection)
Definition at line 11033 of file stm32f4xx.h.
Referenced by TIM_SelectOutputTrigger().
| #define TIM_CR2_MMS_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 11034 of file stm32f4xx.h.
| #define TIM_CR2_MMS_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 11035 of file stm32f4xx.h.
| #define TIM_CR2_MMS_2 ((uint16_t)0x0040) |
Bit 2
Definition at line 11036 of file stm32f4xx.h.
| #define TIM_CR2_OIS1 ((uint16_t)0x0100) |
Output Idle state 1 (OC1 output)
Definition at line 11039 of file stm32f4xx.h.
Referenced by TIM_OC1Init().
| #define TIM_CR2_OIS1N ((uint16_t)0x0200) |
Output Idle state 1 (OC1N output)
Definition at line 11040 of file stm32f4xx.h.
Referenced by TIM_OC1Init().
| #define TIM_CR2_OIS2 ((uint16_t)0x0400) |
Output Idle state 2 (OC2 output)
Definition at line 11041 of file stm32f4xx.h.
Referenced by TIM_OC2Init().
| #define TIM_CR2_OIS2N ((uint16_t)0x0800) |
Output Idle state 2 (OC2N output)
Definition at line 11042 of file stm32f4xx.h.
Referenced by TIM_OC2Init().
| #define TIM_CR2_OIS3 ((uint16_t)0x1000) |
Output Idle state 3 (OC3 output)
Definition at line 11043 of file stm32f4xx.h.
Referenced by TIM_OC3Init().
| #define TIM_CR2_OIS3N ((uint16_t)0x2000) |
Output Idle state 3 (OC3N output)
Definition at line 11044 of file stm32f4xx.h.
Referenced by TIM_OC3Init().
| #define TIM_CR2_OIS4 ((uint16_t)0x4000) |
Output Idle state 4 (OC4 output)
Definition at line 11045 of file stm32f4xx.h.
Referenced by TIM_OC4Init().
| #define TIM_CR2_TI1S ((uint16_t)0x0080) |
| #define TIM_DCR_DBA ((uint16_t)0x001F) |
DBA[4:0] bits (DMA Base Address)
Definition at line 11280 of file stm32f4xx.h.
| #define TIM_DCR_DBA_0 ((uint16_t)0x0001) |
Bit 0
Definition at line 11281 of file stm32f4xx.h.
| #define TIM_DCR_DBA_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 11282 of file stm32f4xx.h.
| #define TIM_DCR_DBA_2 ((uint16_t)0x0004) |
Bit 2
Definition at line 11283 of file stm32f4xx.h.
| #define TIM_DCR_DBA_3 ((uint16_t)0x0008) |
Bit 3
Definition at line 11284 of file stm32f4xx.h.
| #define TIM_DCR_DBA_4 ((uint16_t)0x0010) |
Bit 4
Definition at line 11285 of file stm32f4xx.h.
| #define TIM_DCR_DBL ((uint16_t)0x1F00) |
DBL[4:0] bits (DMA Burst Length)
Definition at line 11287 of file stm32f4xx.h.
| #define TIM_DCR_DBL_0 ((uint16_t)0x0100) |
Bit 0
Definition at line 11288 of file stm32f4xx.h.
| #define TIM_DCR_DBL_1 ((uint16_t)0x0200) |
Bit 1
Definition at line 11289 of file stm32f4xx.h.
| #define TIM_DCR_DBL_2 ((uint16_t)0x0400) |
Bit 2
Definition at line 11290 of file stm32f4xx.h.
| #define TIM_DCR_DBL_3 ((uint16_t)0x0800) |
Bit 3
Definition at line 11291 of file stm32f4xx.h.
| #define TIM_DCR_DBL_4 ((uint16_t)0x1000) |
Bit 4
Definition at line 11292 of file stm32f4xx.h.
| #define TIM_DIER_BIE ((uint16_t)0x0080) |
Break interrupt enable
Definition at line 11081 of file stm32f4xx.h.
| #define TIM_DIER_CC1DE ((uint16_t)0x0200) |
Capture/Compare 1 DMA request enable
Definition at line 11083 of file stm32f4xx.h.
| #define TIM_DIER_CC1IE ((uint16_t)0x0002) |
Capture/Compare 1 interrupt enable
Definition at line 11075 of file stm32f4xx.h.
| #define TIM_DIER_CC2DE ((uint16_t)0x0400) |
Capture/Compare 2 DMA request enable
Definition at line 11084 of file stm32f4xx.h.
| #define TIM_DIER_CC2IE ((uint16_t)0x0004) |
Capture/Compare 2 interrupt enable
Definition at line 11076 of file stm32f4xx.h.
| #define TIM_DIER_CC3DE ((uint16_t)0x0800) |
Capture/Compare 3 DMA request enable
Definition at line 11085 of file stm32f4xx.h.
| #define TIM_DIER_CC3IE ((uint16_t)0x0008) |
Capture/Compare 3 interrupt enable
Definition at line 11077 of file stm32f4xx.h.
| #define TIM_DIER_CC4DE ((uint16_t)0x1000) |
Capture/Compare 4 DMA request enable
Definition at line 11086 of file stm32f4xx.h.
| #define TIM_DIER_CC4IE ((uint16_t)0x0010) |
Capture/Compare 4 interrupt enable
Definition at line 11078 of file stm32f4xx.h.
| #define TIM_DIER_COMDE ((uint16_t)0x2000) |
COM DMA request enable
Definition at line 11087 of file stm32f4xx.h.
| #define TIM_DIER_COMIE ((uint16_t)0x0020) |
COM interrupt enable
Definition at line 11079 of file stm32f4xx.h.
| #define TIM_DIER_TDE ((uint16_t)0x4000) |
Trigger DMA request enable
Definition at line 11088 of file stm32f4xx.h.
| #define TIM_DIER_TIE ((uint16_t)0x0040) |
Trigger interrupt enable
Definition at line 11080 of file stm32f4xx.h.
| #define TIM_DIER_UDE ((uint16_t)0x0100) |
Update DMA request enable
Definition at line 11082 of file stm32f4xx.h.
| #define TIM_DIER_UIE ((uint16_t)0x0001) |
Update interrupt enable
Definition at line 11074 of file stm32f4xx.h.
| #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) |
DMA register for burst accesses
Definition at line 11295 of file stm32f4xx.h.
| #define TIM_EGR_BG ((uint8_t)0x80) |
Break Generation
Definition at line 11112 of file stm32f4xx.h.
| #define TIM_EGR_CC1G ((uint8_t)0x02) |
Capture/Compare 1 Generation
Definition at line 11106 of file stm32f4xx.h.
| #define TIM_EGR_CC2G ((uint8_t)0x04) |
Capture/Compare 2 Generation
Definition at line 11107 of file stm32f4xx.h.
| #define TIM_EGR_CC3G ((uint8_t)0x08) |
Capture/Compare 3 Generation
Definition at line 11108 of file stm32f4xx.h.
| #define TIM_EGR_CC4G ((uint8_t)0x10) |
Capture/Compare 4 Generation
Definition at line 11109 of file stm32f4xx.h.
| #define TIM_EGR_COMG ((uint8_t)0x20) |
Capture/Compare Control Update Generation
Definition at line 11110 of file stm32f4xx.h.
| #define TIM_EGR_TG ((uint8_t)0x40) |
Trigger Generation
Definition at line 11111 of file stm32f4xx.h.
| #define TIM_EGR_UG ((uint8_t)0x01) |
Update Generation
Definition at line 11105 of file stm32f4xx.h.
| #define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) |
ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap)
Definition at line 11301 of file stm32f4xx.h.
| #define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) |
Bit 0
Definition at line 11302 of file stm32f4xx.h.
| #define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) |
Bit 1
Definition at line 11303 of file stm32f4xx.h.
| #define TIM_OR_TI4_RMP ((uint16_t)0x00C0) |
TI4_RMP[1:0] bits (TIM5 Input 4 remap)
Definition at line 11298 of file stm32f4xx.h.
| #define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) |
Bit 0
Definition at line 11299 of file stm32f4xx.h.
| #define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) |
Bit 1
Definition at line 11300 of file stm32f4xx.h.
| #define TIM_PSC_PSC ((uint16_t)0xFFFF) |
Prescaler Value
Definition at line 11237 of file stm32f4xx.h.
| #define TIM_RCR_REP ((uint8_t)0xFF) |
Repetition Counter Value
Definition at line 11243 of file stm32f4xx.h.
| #define TIM_SMCR_ECE ((uint16_t)0x4000) |
External clock enable
Definition at line 11070 of file stm32f4xx.h.
Referenced by TIM_ETRClockMode2Config().
| #define TIM_SMCR_ETF ((uint16_t)0x0F00) |
ETF[3:0] bits (External trigger filter)
Definition at line 11060 of file stm32f4xx.h.
| #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) |
Bit 0
Definition at line 11061 of file stm32f4xx.h.
| #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) |
Bit 1
Definition at line 11062 of file stm32f4xx.h.
| #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) |
Bit 2
Definition at line 11063 of file stm32f4xx.h.
| #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) |
Bit 3
Definition at line 11064 of file stm32f4xx.h.
| #define TIM_SMCR_ETP ((uint16_t)0x8000) |
External trigger polarity
Definition at line 11071 of file stm32f4xx.h.
| #define TIM_SMCR_ETPS ((uint16_t)0x3000) |
ETPS[1:0] bits (External trigger prescaler)
Definition at line 11066 of file stm32f4xx.h.
| #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) |
Bit 0
Definition at line 11067 of file stm32f4xx.h.
| #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) |
Bit 1
Definition at line 11068 of file stm32f4xx.h.
| #define TIM_SMCR_MSM ((uint16_t)0x0080) |
Master/slave mode
Definition at line 11058 of file stm32f4xx.h.
Referenced by TIM_SelectMasterSlaveMode().
| #define TIM_SMCR_SMS ((uint16_t)0x0007) |
SMS[2:0] bits (Slave mode selection)
Definition at line 11048 of file stm32f4xx.h.
Referenced by TIM_EncoderInterfaceConfig(), TIM_ETRClockMode1Config(), TIM_InternalClockConfig(), and TIM_SelectSlaveMode().
| #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) |
Bit 0
Definition at line 11049 of file stm32f4xx.h.
| #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 11050 of file stm32f4xx.h.
| #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) |
Bit 2
Definition at line 11051 of file stm32f4xx.h.
| #define TIM_SMCR_TS ((uint16_t)0x0070) |
TS[2:0] bits (Trigger selection)
Definition at line 11053 of file stm32f4xx.h.
Referenced by TIM_ETRClockMode1Config(), and TIM_SelectInputTrigger().
| #define TIM_SMCR_TS_0 ((uint16_t)0x0010) |
Bit 0
Definition at line 11054 of file stm32f4xx.h.
| #define TIM_SMCR_TS_1 ((uint16_t)0x0020) |
Bit 1
Definition at line 11055 of file stm32f4xx.h.
| #define TIM_SMCR_TS_2 ((uint16_t)0x0040) |
Bit 2
Definition at line 11056 of file stm32f4xx.h.
| #define TIM_SR_BIF ((uint16_t)0x0080) |
Break interrupt Flag
Definition at line 11098 of file stm32f4xx.h.
| #define TIM_SR_CC1IF ((uint16_t)0x0002) |
Capture/Compare 1 interrupt Flag
Definition at line 11092 of file stm32f4xx.h.
| #define TIM_SR_CC1OF ((uint16_t)0x0200) |
Capture/Compare 1 Overcapture Flag
Definition at line 11099 of file stm32f4xx.h.
| #define TIM_SR_CC2IF ((uint16_t)0x0004) |
Capture/Compare 2 interrupt Flag
Definition at line 11093 of file stm32f4xx.h.
| #define TIM_SR_CC2OF ((uint16_t)0x0400) |
Capture/Compare 2 Overcapture Flag
Definition at line 11100 of file stm32f4xx.h.
| #define TIM_SR_CC3IF ((uint16_t)0x0008) |
Capture/Compare 3 interrupt Flag
Definition at line 11094 of file stm32f4xx.h.
| #define TIM_SR_CC3OF ((uint16_t)0x0800) |
Capture/Compare 3 Overcapture Flag
Definition at line 11101 of file stm32f4xx.h.
| #define TIM_SR_CC4IF ((uint16_t)0x0010) |
Capture/Compare 4 interrupt Flag
Definition at line 11095 of file stm32f4xx.h.
| #define TIM_SR_CC4OF ((uint16_t)0x1000) |
Capture/Compare 4 Overcapture Flag
Definition at line 11102 of file stm32f4xx.h.
| #define TIM_SR_COMIF ((uint16_t)0x0020) |
COM interrupt Flag
Definition at line 11096 of file stm32f4xx.h.
| #define TIM_SR_TIF ((uint16_t)0x0040) |
Trigger interrupt Flag
Definition at line 11097 of file stm32f4xx.h.
| #define TIM_SR_UIF ((uint16_t)0x0001) |
Update interrupt Flag
Definition at line 11091 of file stm32f4xx.h.
| #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) |
Fraction of USARTDIV
Definition at line 11415 of file stm32f4xx.h.
| #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) |
Mantissa of USARTDIV
Definition at line 11416 of file stm32f4xx.h.
| #define USART_CR1_IDLEIE ((uint16_t)0x0010) |
IDLE Interrupt Enable
Definition at line 11423 of file stm32f4xx.h.
| #define USART_CR1_M ((uint16_t)0x1000) |
Word length
Definition at line 11431 of file stm32f4xx.h.
| #define USART_CR1_OVER8 ((uint16_t)0x8000) |
USART Oversampling by 8 enable
Definition at line 11433 of file stm32f4xx.h.
Referenced by USART_Init(), and USART_OverSampling8Cmd().
| #define USART_CR1_PCE ((uint16_t)0x0400) |
Parity Control Enable
Definition at line 11429 of file stm32f4xx.h.
| #define USART_CR1_PEIE ((uint16_t)0x0100) |
PE Interrupt Enable
Definition at line 11427 of file stm32f4xx.h.
| #define USART_CR1_PS ((uint16_t)0x0200) |
Parity Selection
Definition at line 11428 of file stm32f4xx.h.
| #define USART_CR1_RE ((uint16_t)0x0004) |
Receiver Enable
Definition at line 11421 of file stm32f4xx.h.
| #define USART_CR1_RWU ((uint16_t)0x0002) |
Receiver wakeup
Definition at line 11420 of file stm32f4xx.h.
Referenced by USART_ReceiverWakeUpCmd().
| #define USART_CR1_RXNEIE ((uint16_t)0x0020) |
RXNE Interrupt Enable
Definition at line 11424 of file stm32f4xx.h.
| #define USART_CR1_SBK ((uint16_t)0x0001) |
| #define USART_CR1_TCIE ((uint16_t)0x0040) |
Transmission Complete Interrupt Enable
Definition at line 11425 of file stm32f4xx.h.
| #define USART_CR1_TE ((uint16_t)0x0008) |
Transmitter Enable
Definition at line 11422 of file stm32f4xx.h.
| #define USART_CR1_TXEIE ((uint16_t)0x0080) |
PE Interrupt Enable
Definition at line 11426 of file stm32f4xx.h.
| #define USART_CR1_UE ((uint16_t)0x2000) |
| #define USART_CR1_WAKE ((uint16_t)0x0800) |
| #define USART_CR2_ADD ((uint16_t)0x000F) |
Address of the USART node
Definition at line 11436 of file stm32f4xx.h.
Referenced by USART_SetAddress().
| #define USART_CR2_CLKEN ((uint16_t)0x0800) |
Clock Enable
Definition at line 11442 of file stm32f4xx.h.
| #define USART_CR2_CPHA ((uint16_t)0x0200) |
Clock Phase
Definition at line 11440 of file stm32f4xx.h.
| #define USART_CR2_CPOL ((uint16_t)0x0400) |
Clock Polarity
Definition at line 11441 of file stm32f4xx.h.
| #define USART_CR2_LBCL ((uint16_t)0x0100) |
Last Bit Clock pulse
Definition at line 11439 of file stm32f4xx.h.
| #define USART_CR2_LBDIE ((uint16_t)0x0040) |
LIN Break Detection Interrupt Enable
Definition at line 11438 of file stm32f4xx.h.
| #define USART_CR2_LBDL ((uint16_t)0x0020) |
LIN Break Detection Length
Definition at line 11437 of file stm32f4xx.h.
Referenced by USART_LINBreakDetectLengthConfig().
| #define USART_CR2_LINEN ((uint16_t)0x4000) |
| #define USART_CR2_STOP ((uint16_t)0x3000) |
STOP[1:0] bits (STOP bits)
Definition at line 11444 of file stm32f4xx.h.
Referenced by USART_Init().
| #define USART_CR2_STOP_0 ((uint16_t)0x1000) |
Bit 0
Definition at line 11445 of file stm32f4xx.h.
| #define USART_CR2_STOP_1 ((uint16_t)0x2000) |
Bit 1
Definition at line 11446 of file stm32f4xx.h.
| #define USART_CR3_CTSE ((uint16_t)0x0200) |
CTS Enable
Definition at line 11460 of file stm32f4xx.h.
| #define USART_CR3_CTSIE ((uint16_t)0x0400) |
CTS Interrupt Enable
Definition at line 11461 of file stm32f4xx.h.
| #define USART_CR3_DMAR ((uint16_t)0x0040) |
DMA Enable Receiver
Definition at line 11457 of file stm32f4xx.h.
| #define USART_CR3_DMAT ((uint16_t)0x0080) |
DMA Enable Transmitter
Definition at line 11458 of file stm32f4xx.h.
| #define USART_CR3_EIE ((uint16_t)0x0001) |
Error Interrupt Enable
Definition at line 11451 of file stm32f4xx.h.
| #define USART_CR3_HDSEL ((uint16_t)0x0008) |
Half-Duplex Selection
Definition at line 11454 of file stm32f4xx.h.
Referenced by USART_HalfDuplexCmd().
| #define USART_CR3_IREN ((uint16_t)0x0002) |
| #define USART_CR3_IRLP ((uint16_t)0x0004) |
| #define USART_CR3_NACK ((uint16_t)0x0010) |
Smartcard NACK enable
Definition at line 11455 of file stm32f4xx.h.
Referenced by USART_SmartCardNACKCmd().
| #define USART_CR3_ONEBIT ((uint16_t)0x0800) |
USART One bit method enable
Definition at line 11462 of file stm32f4xx.h.
Referenced by USART_OneBitMethodCmd().
| #define USART_CR3_RTSE ((uint16_t)0x0100) |
RTS Enable
Definition at line 11459 of file stm32f4xx.h.
| #define USART_CR3_SCEN ((uint16_t)0x0020) |
Smartcard mode enable
Definition at line 11456 of file stm32f4xx.h.
Referenced by USART_SmartCardCmd().
| #define USART_DR_DR ((uint16_t)0x01FF) |
Data value
Definition at line 11412 of file stm32f4xx.h.
| #define USART_GTPR_GT ((uint16_t)0xFF00) |
| #define USART_GTPR_PSC ((uint16_t)0x00FF) |
PSC[7:0] bits (Prescaler value)
Definition at line 11465 of file stm32f4xx.h.
Referenced by USART_SetGuardTime().
| #define USART_GTPR_PSC_0 ((uint16_t)0x0001) |
Bit 0
Definition at line 11466 of file stm32f4xx.h.
| #define USART_GTPR_PSC_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 11467 of file stm32f4xx.h.
| #define USART_GTPR_PSC_2 ((uint16_t)0x0004) |
Bit 2
Definition at line 11468 of file stm32f4xx.h.
| #define USART_GTPR_PSC_3 ((uint16_t)0x0008) |
Bit 3
Definition at line 11469 of file stm32f4xx.h.
| #define USART_GTPR_PSC_4 ((uint16_t)0x0010) |
Bit 4
Definition at line 11470 of file stm32f4xx.h.
| #define USART_GTPR_PSC_5 ((uint16_t)0x0020) |
Bit 5
Definition at line 11471 of file stm32f4xx.h.
| #define USART_GTPR_PSC_6 ((uint16_t)0x0040) |
Bit 6
Definition at line 11472 of file stm32f4xx.h.
| #define USART_GTPR_PSC_7 ((uint16_t)0x0080) |
Bit 7
Definition at line 11473 of file stm32f4xx.h.
| #define USART_SR_CTS ((uint16_t)0x0200) |
CTS Flag
Definition at line 11409 of file stm32f4xx.h.
| #define USART_SR_FE ((uint16_t)0x0002) |
Framing Error
Definition at line 11401 of file stm32f4xx.h.
| #define USART_SR_IDLE ((uint16_t)0x0010) |
IDLE line detected
Definition at line 11404 of file stm32f4xx.h.
| #define USART_SR_LBD ((uint16_t)0x0100) |
LIN Break Detection Flag
Definition at line 11408 of file stm32f4xx.h.
| #define USART_SR_NE ((uint16_t)0x0004) |
Noise Error Flag
Definition at line 11402 of file stm32f4xx.h.
| #define USART_SR_ORE ((uint16_t)0x0008) |
OverRun Error
Definition at line 11403 of file stm32f4xx.h.
| #define USART_SR_PE ((uint16_t)0x0001) |
Parity Error
Definition at line 11400 of file stm32f4xx.h.
| #define USART_SR_RXNE ((uint16_t)0x0020) |
Read Data Register Not Empty
Definition at line 11405 of file stm32f4xx.h.
| #define USART_SR_TC ((uint16_t)0x0040) |
Transmission Complete
Definition at line 11406 of file stm32f4xx.h.
| #define USART_SR_TXE ((uint16_t)0x0080) |
Transmit Data Register Empty
Definition at line 11407 of file stm32f4xx.h.
| #define WWDG_CFR_EWI ((uint16_t)0x0200) |
Early Wakeup Interrupt
Definition at line 11527 of file stm32f4xx.h.
| #define WWDG_CFR_W ((uint16_t)0x007F) |
W[6:0] bits (7-bit window value)
Definition at line 11503 of file stm32f4xx.h.
| #define WWDG_CFR_W0 WWDG_CFR_W_0 |
Definition at line 11512 of file stm32f4xx.h.
| #define WWDG_CFR_W1 WWDG_CFR_W_1 |
Definition at line 11513 of file stm32f4xx.h.
| #define WWDG_CFR_W2 WWDG_CFR_W_2 |
Definition at line 11514 of file stm32f4xx.h.
| #define WWDG_CFR_W3 WWDG_CFR_W_3 |
Definition at line 11515 of file stm32f4xx.h.
| #define WWDG_CFR_W4 WWDG_CFR_W_4 |
Definition at line 11516 of file stm32f4xx.h.
| #define WWDG_CFR_W5 WWDG_CFR_W_5 |
Definition at line 11517 of file stm32f4xx.h.
| #define WWDG_CFR_W6 WWDG_CFR_W_6 |
Definition at line 11518 of file stm32f4xx.h.
| #define WWDG_CFR_W_0 ((uint16_t)0x0001) |
Bit 0
Definition at line 11504 of file stm32f4xx.h.
| #define WWDG_CFR_W_1 ((uint16_t)0x0002) |
Bit 1
Definition at line 11505 of file stm32f4xx.h.
| #define WWDG_CFR_W_2 ((uint16_t)0x0004) |
Bit 2
Definition at line 11506 of file stm32f4xx.h.
| #define WWDG_CFR_W_3 ((uint16_t)0x0008) |
Bit 3
Definition at line 11507 of file stm32f4xx.h.
| #define WWDG_CFR_W_4 ((uint16_t)0x0010) |
Bit 4
Definition at line 11508 of file stm32f4xx.h.
| #define WWDG_CFR_W_5 ((uint16_t)0x0020) |
Bit 5
Definition at line 11509 of file stm32f4xx.h.
| #define WWDG_CFR_W_6 ((uint16_t)0x0040) |
Bit 6
Definition at line 11510 of file stm32f4xx.h.
| #define WWDG_CFR_WDGTB ((uint16_t)0x0180) |
WDGTB[1:0] bits (Timer Base)
Definition at line 11520 of file stm32f4xx.h.
| #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 |
Definition at line 11524 of file stm32f4xx.h.
| #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 |
Definition at line 11525 of file stm32f4xx.h.
| #define WWDG_CFR_WDGTB_0 ((uint16_t)0x0080) |
Bit 0
Definition at line 11521 of file stm32f4xx.h.
| #define WWDG_CFR_WDGTB_1 ((uint16_t)0x0100) |
Bit 1
Definition at line 11522 of file stm32f4xx.h.
| #define WWDG_CR_T ((uint8_t)0x7F) |
T[6:0] bits (7-Bit counter (MSB to LSB))
Definition at line 11483 of file stm32f4xx.h.
| #define WWDG_CR_T0 WWDG_CR_T_0 |
Definition at line 11492 of file stm32f4xx.h.
| #define WWDG_CR_T1 WWDG_CR_T_1 |
Definition at line 11493 of file stm32f4xx.h.
| #define WWDG_CR_T2 WWDG_CR_T_2 |
Definition at line 11494 of file stm32f4xx.h.
| #define WWDG_CR_T3 WWDG_CR_T_3 |
Definition at line 11495 of file stm32f4xx.h.
| #define WWDG_CR_T4 WWDG_CR_T_4 |
Definition at line 11496 of file stm32f4xx.h.
| #define WWDG_CR_T5 WWDG_CR_T_5 |
Definition at line 11497 of file stm32f4xx.h.
| #define WWDG_CR_T6 WWDG_CR_T_6 |
Definition at line 11498 of file stm32f4xx.h.
| #define WWDG_CR_T_0 ((uint8_t)0x01) |
Bit 0
Definition at line 11484 of file stm32f4xx.h.
| #define WWDG_CR_T_1 ((uint8_t)0x02) |
Bit 1
Definition at line 11485 of file stm32f4xx.h.
| #define WWDG_CR_T_2 ((uint8_t)0x04) |
Bit 2
Definition at line 11486 of file stm32f4xx.h.
| #define WWDG_CR_T_3 ((uint8_t)0x08) |
Bit 3
Definition at line 11487 of file stm32f4xx.h.
| #define WWDG_CR_T_4 ((uint8_t)0x10) |
Bit 4
Definition at line 11488 of file stm32f4xx.h.
| #define WWDG_CR_T_5 ((uint8_t)0x20) |
Bit 5
Definition at line 11489 of file stm32f4xx.h.
| #define WWDG_CR_T_6 ((uint8_t)0x40) |
Bit 6
Definition at line 11490 of file stm32f4xx.h.
| #define WWDG_CR_WDGA ((uint8_t)0x80) |
| #define WWDG_SR_EWIF ((uint8_t)0x01) |
Early Wakeup Interrupt Flag
Definition at line 11530 of file stm32f4xx.h.